R
Spartan-II FPGA Family: Functional Description
Revision History
Date
09/18/00
03/05/01
09/03/03
Version
2.0
2.1
2.2
Description
Sectioned the Spartan-II Family data sheet into four modules. Corrected banking description.
Clarified guidelines for applying power to V
CCINT
and V
CCO
The following changes were made:
•
•
•
•
•
06/13/08
2.8
cautions about toggling WRITE during serial configuration.
Maximum V
IH
values in
and
changed to 5.5V.
In
removed sentence about lack of INTEST support.
In
added note about the state of I/Os after power-on.
In
explained configuration bit alignment to SelectMap
port.
Added note that TDI, TMS, and TCK have a default pull-up resistor. Added note on maximum
daisy chain limit. Updated
and
since Mode pins can be pulled up to either
2.5V or 3.3V. Updated DLL section. Recommended using property or attribute instead of
primitive to define I/O properties. Updated description and links. Updated all modules for
continuous page, figure, and table numbering. Synchronized all modules to v2.8.
DS001-2 (v2.8) June 13, 2008
Product Specification
Module 2 of 4
50
XILINX [ XILINX, INC ]
