R
Spartan-II FPGA Family: Functional Description
PCI33_3 and PCI66_3
PCI33_3 or PCI66_3 require no termination. DC voltage
specifications appear in
for the PCI33_3 and
PCI66_3 standards. See
in Module 3
for the actual FPGA characteristics.
Table 30:
PCI33_3 and PCI66_3 Voltage Specifications
V
TT
= 1.5V
CTT
A sample circuit illustrating a valid termination technique for
CTT appear in
DC voltage specifications appear
in
for the CTT standard. See
in
Module 3 for the actual FPGA characteristics .
CTT
V
CCO
= 3.3V
50Ω
Z = 50
Parameter
V
CCO
V
REF
V
TT
V
IH
= 0.5
×
V
CCO
V
IL
= 0.3
×
V
CCO
V
OH
= 0.9
×
V
CCO
V
OL
= 0.1
×
V
CCO
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA)
Min
3.0
-
-
1.5
–0.5
2.7
-
Note 1
Note 1
Typ
3.3
-
-
1.65
0.99
-
-
-
-
Max
3.6
-
-
V
CCO
+ 0.5
1.08
-
0.36
-
-
V
REF
= 1.5V
DS001_51_061200
Figure 51:
Terminated CTT
Table 29:
CTT Voltage Specifications
Parameter
V
CCO
V
REF
V
TT
V
IH
≥
V
REF
+ 0.2
V
IL
≤
V
REF
– 0.2
V
OH
≥
V
REF
+ 0.4
V
OL
≤
V
REF
– 0.4
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA)
Min
2.05
(1)
1.35
1.35
1.55
-
1.75
-
–8
8
Typ
3.3
1.5
1.5
1.7
1.3
1.9
1.1
-
-
Max
3.6
1.65
1.65
-
1.45
-
1.25
-
-
Notes:
1. Tested according to the relevant specification.
PCI33_5
PCI33_5 requires no termination. DC voltage specifications
appear in
for the PCI33_5 standard. See
in Module 3 for the actual FPGA
characteristics.
Table 31:
PCI33_5 Voltage Specifications
Parameter
V
CCO
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA)
Min
3.0
-
-
1.425
–0.5
2.4
-
Note 1
Note 1
Typ
3.3
-
-
1.5
1.0
-
-
-
-
Max
3.6
-
-
5.5
1.05
-
0.55
-
-
Notes:
1. Timing delays are calculated based on V
CCO
min of 3.0V.
Notes:
1. Tested according to the relevant specification.
DS001-2 (v2.8) June 13, 2008
Product Specification
Module 2 of 4
48
XILINX [ XILINX, INC ]
