R
Spartan-II FPGA Family: Functional Description
SSTL2 Class II
A sample circuit illustrating a valid termination technique for
SSTL2_II appears in
DC voltage specifications
appear in
for the SSTL2_II standard. See
in Module 3 for the actual FPGA
characteristics.
SSTL2 Class II
V
TT
= 1.25V
V
TT
= 1.25V
V
CCO
= 2.5V
50Ω
25Ω
Z = 50
SSTL2_I
A sample circuit illustrating a valid termination technique for
SSTL2_I appears in
DC voltage specifications
appear in
for the SSTL2_I standard. See
in Module 3 for the actual FPGA
characteristics
SSTL2 Class I
V
CCO
= 2.5V
V
TT
= 1.25V
50Ω
Z = 50
50Ω
25Ω
V
REF
= 1.25V
DS001_49_061200
V
REF
= 1.25V
DS001_50_061200
Figure 49:
Terminated SSTL2 Class I
Table 27:
SSTL2_I Voltage Specifications
Parameter
V
CCO
V
REF
= 0.5
×
V
CCO
V
TT
= V
REF
+ N
(1)
V
IH
≥
V
REF
+ 0.18
V
IL
≤
V
REF
– 0.18
V
OH
≥
V
REF
+ 0.61
V
OL
≤
V
REF
– 0.61
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA)
Min
2.3
1.15
1.11
1.33
–0.3
(3)
1.76
-
–7.6
7.6
Typ
2.5
1.25
1.25
1.43
1.07
-
-
-
-
Max
2.7
1.35
1.39
3.0
(2)
1.17
-
0.74
-
-
V
CCO
Figure 50:
Terminated SSTL2 Class II
Table 28:
SSTL2_II Voltage Specifications
Parameter
V
REF
= 0.5
×
V
CCO
V
TT
= V
REF
+ N
(1)
V
IH
≥
V
REF
+ 0.18
V
IL
≤
V
REF
– 0.18
V
OH
≥
V
REF
+ 0.8
V
OL
≤
V
REF
- 0.8
I
OH
at V
OH
(mA)
I
OL
at V
OL
(mA)
Min
2.3
1.15
1.11
1.33
–0.3
(3)
1.95
-
–15.2
15.2
Typ
2.5
1.25
1.25
1.43
1.07
-
-
-
-
Max
2.7
1.35
1.39
3.0
(2)
1.17
-
0.55
-
-
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. V
IH
maximum is V
CCO
+ 0.3.
3. V
IL
minimum does not conform to the formula.
Notes:
1. N must be greater than or equal to –0.04 and less than or
equal to 0.04.
2. V
IH
maximum is V
CCO
+ 0.3.
3. V
IL
minimum does not conform to the formula.
DS001-2 (v2.8) June 13, 2008
Product Specification
Module 2 of 4
47
XILINX [ XILINX, INC ]
