OPB 16450 UART
•
System clock frequency of 100 MHz
UART Background
The OPB 16450 performs parallel to serial conversion on characters received from the CPU and serial to parallel conversion
on characters received from a modem or microprocessor peripheral.
The OPB 16450 is capable of transmitting and receiving 8, 7, 6, or 5 bit characters, with 2, 1.5 or 1 stop bits and odd, even
or no parity. The OPB 16450 can transmit and receive independently.
The device can be configured and it’s status monitored via the internal register set. The OPB 16450 is capable of signaling
receiver, transmitter and modem control interrupts. These interrupts can be masked, are prioritized and can be identified by
reading an internal register.
16450 UART Design Parameters
To allow you to obtain an OPB UART that is uniquely tailored for your system, certain features can be parameterized in the
OPB UART design. This allows you to have a design that only utilizes the resources required by your system and runs at the
best possible performance. The features that can be parameterized in the Xilinx OPB UART design are shown in
Table 1:
Design Parameters
Grouping /
Number
OPB
Interface
G1
Feature /
Description
OPB UART Base
Address
Parameter Name
C_BASEADDR
Allowable Values
Valid Word Aligned
Address.
C_BASEADDR must be
a multiple of the range,
where the range is
C_HIGHADDR -
C_BASEADDR +1.
Default
Value
A0000000
VHDL Type
std_logic_vector
G2
G3
G4
G5
G6
OPB Data Bus
Width
OPB Address Bus
Width
Device Block ID
(1)
C_OPB_DWIDTH
C_OPB_AWIDTH
C_DEV_BLK_ID
32
32
0-255
0,1.
32
32
0
0
integer
integer
integer
integer
std_logic_vector
Module Identification C_DEV_MIR_ENABLE
Register
(1)
OPB UART High
Address
C_HIGHADDR
C_HIGHADDR
A0001FFF
-C_BASEADDR must
be a power of 2 >= to
C_BASEADDR+1FF
F
0
0
1
UART
Features
G7
G8
G9
External XIN
External RCLK
Select UART
C_HAS_EXTERNAL_X 0,1
IN
C_HAS_EXTERNAL_
RCLK
C_IS_A_16550
0,1
0,1
integer
integer
integer
2
1-800-255-7778
DS433 August 18, 2004
Product Specification
XILINX [ XILINX, INC ]
