OPB 16450 UART
These pins are sampled when AdsN is low and held when AdsN is high. If AdsN is tied low, A(2:0) must be stable while
Rd/RdN/Wr/WrN are active.
Cs0, Cs1, Cs2N. UART chip selects. These pins are sampled when AdsN is low and held when AdsN is high. If AdsN is tied
low, these pins must be stable while Rd/RdN/Wr/WrN are active.
All other signals. All other interface signals are as described in the National Semiconductor PC16550D UART with FIFOs
data sheet (June, 1995). (http://www.national.com/pf/PC/PC16550D.html).
Design Implementation
Target Technology
The intended target technology is Virtex-II FPGA
Device Utilization and Timing
OPB_Clk is capable of running at 100 MHz. XIN and RCLK must be less than 1/2 OPB_Clk frequency.
Performance Benchmarks
Table 16: Performance and Resource Utilization Benchmarks
Parameter Values
Device Resources
f
(MHz)
MAX
Slices
341
Slice
Flip-Flops
LUTs
357
f
MAX
OPB UART 16450
N/A
N/A
Specification Exceptions
System Clock
The asynchronous microprocessor interface of the National Semiconductor PC16550D is synchronized to the system clock
input of the UART.
Register Addresses
All internal registers reside on a 32 bit word boundary not on 8 bit byte boundaries.
Reference Documents
The following documents contain reference information important to understanding the UART design:
•
National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995).
(http://www.national.com/pf/PC/PC16550D.html)
14
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Product Specification
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