R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 11
First Address Latching Sequence
VDD/VDDQ
TVHRWZ
READY_WAIT
TRWRT
Latency cycles (default = 7)
G
L
TRWHKL
TAVKH3
1
TKH3AX
K
2
3
4
Address
Address not Valid
A22–A0
TKHQV
FFFFh (Sync + Dummy cycle)
D0 D1 D2 D3 D4 D5
DQ15–DQ0
DS617_44_053008
Notes:
1. W is tied High.
2. Address is latched on the third rising edge of K when G and E are Low, and L and READY_WAIT are High.
3. READY_WAIT requires an external pull-up resistor to V sufficiently strong to ensure a clean Low-to-High transition within less than T
DDQ
RWRT
when the READY_WAIT pin is released to a high-impedance state.
Figure 11: Power-Up
X-Ref Target - Figure 12
VDD/VDDQ
TVHRWZ
TRWRT
READY_WAIT
G
L
K
TAVRWH
TRWHAX
2
3
4
K1
Valid Address
TKHQV
A22-A0
FFFFh
D0 D1 D2 D3 D4 D5 D6 D7 D8
DQ15-DQ0
Latency Cycles
(default = 7)
DS617_45_101508
Notes:
1. It is recommended to use the shown timings in the case of a free-running clock.
2. W is tied High.
3. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at V and G at V ).
IH
IL
Figure 12: Power-Up (Free-Running Clock)
DS617 (v3.0.1) January 07, 2010
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Product Specification
29
XILINX [ XILINX, INC ]
