R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 13
TRWLRWH
READY_WAIT
G
L, W
High
Latency Cycles
(default = 7)
TRWHKL
K
1
2
3
4
TAVKH3
TKH3AX
Valid
A22-A0
DQ15-DQ0
Address
TKHQV
FFFFh
Dk Dn
DATA VALID
FFFFh
D0 D1 D2 D3 D4 D5
DATA VALID
DS617_46_100608
Notes:
1. Dk and Dn indicate the Data valid after k and n clock cycles, respectively.
2. This figure applies when READY_WAIT (CR4) is configured with the Ready function.
Figure 13: READY_WAIT Pulse (Clock is not Free Running)
X-Ref Target - Figure 14
TPLPH
RP
READY_WAIT
TPHRWZ
TRWRT
TPLRWL
Low
G
High
L, W
TAVRWH
TRWHAX
K
K1
2
3
4
Valid Address
FFFFh
A22–A0
TKHQV
D0
D1
D2
D3
D4
D5
D6
D7
D8
FFFFh
DQ15–DQ0
Latency Cycles
(default = 7)
DS617_47_102308
Notes:
1. W is tied High.
2. It is recommended to use the shown timings when the system has a free-running clock.
3. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at V and G at V ).
IH
IL
4. READY_WAIT requires an external pull-up resistor to V
sufficiently strong to ensure a clean Low-to-High transition within less than T
DDQ
RWRT
when the READY_WAIT pin is released to a high-impedance state.
Figure 14: READY_WAIT Pulse (Free-Running Clock)
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
30
XILINX [ XILINX, INC ]
