R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 15
TPLPH
RP
TPLRWL
TPHRWZ TRWRT
READY_WAIT
G
High
L, W
K
Latency Default Cycles
Valid
A22−A0
Address not Valid
Address
TKHQV
DQ15−DQ0
FFFFh
D0 D1 D2 D3 D4 D5
Valid Data
DS617_48_101508
Figure 15: RP Pulse (Clock is not Free Running)
X-Ref Target - Figure 16
TPLPH
RP
TRWRT
READY_WAIT
TPHRWZ
TPLRWL
Low
G
High
L, W
TAVRWH
TRWHAX
K
A22-A0
K1
2
3
4
Valid Address
TKHQV
FFFFh
FFFFh
D0 D1 D2 D3 D4 D5 D6 D7 D8
DQ15-DQ0
Latency Cycles
(default = 7)
DS617_49_101608
Notes:
1. It is recommended to use the shown timings in the case of a free-running clock.
2. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at V and G at V ).
IH
IL
Figure 16: RP Pulse (Free Running Clock)
DS617 (v3.0.1) January 07, 2010
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Product Specification
31
XILINX [ XILINX, INC ]
