R
Platform Flash XL High-Density Configuration and Storage Device
where:
Read Mode Select Bit (CR15)
t is the clock period
K
The Read Select bit, CR15, is used to switch between
Asynchronous and Synchronous Read operations. When
this bit is set to ‘1’, read operations are asynchronous; when
set to ‘0’, read operations are synchronous.
t
is the data setup time required by the
QVK_CPU
system CPU
t
is the clock to data valid time.
KQV
Synchronous Burst Read is supported in both parameter
and main blocks and can be performed across banks.
If this condition is not satisfied, the Data Output
Configuration bit should be set to ‘1’ for two clock cycles
(Figure 9, page 28).
On reset or power-up, the Read Select bit is set to ‘0’ for
synchronous access.
Wait Configuration Bit (CR8)
X-Latency Bits (CR13-CR11)
The Wait Configuration bit is used to control the timing of
the READY_WAIT signal when configured as an output with
the Wait function (in Synchronous Burst Read mode).
The X-Latency bits are used during Synchronous Read
operations to set the number of clock cycles between the
address being latched and the first data becoming available
(Figure 9). For correct operation the X-Latency bits can only
assume the values listed in Table 12, page 26.
When READY_WAIT is asserted, data is not valid; when
READY_WAIT is deasserted, data is valid.
When the Wait Configuration bit is Low (reset to ‘0’), the
READY_WAIT signal (configured as an output with the Wait
function) is asserted during the WAIT state. When the Wait
Configuration bit is High (set to ‘1’), the READY_WAIT
output pin is asserted one data cycle before the WAIT state.
Table 13 shows how to set the X-Latency parameter, taking
into account the speed class of the device and the frequency
used to read the flash memory in synchronous mode.
Table 13: X-latency Settings
FMAX
TKmin
33 ns
25 ns
19 ns
X-Latency min
Burst Type Bit (CR7)
30 MHz
40 MHz
54 MHz
3
4
5
The Burst Type bit determines the sequence of addresses
read during Synchronous Burst Read operations. This bit is
High (set to ‘1’) as the memory outputs from sequential
addresses only.
Wait Polarity Bit (CR10)
See Table 14, page 29, for the sequence of addresses
output from a given starting address in sequential mode.
The Wait Polarity bit is used to set the polarity of the
READY_WAIT signal used in Synchronous Burst Read
mode (with CR4 = 0). During this mode, the READY_WAIT
signal indicates whether the data output is valid or a WAIT
state must be inserted.
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit (CR6) is used to configure the
active edge of the Clock (K) during synchronous read
operations. When this bit is Low (set to ‘0’), the falling edge
of the Clock is the active edge; when High (set to ‘1’), the
rising edge of the Clock is the active edge.
When the Wait Polarity bit is at '0', the READY_WAIT signal
is active Low. When this bit is set to '1', the READY_WAIT
signal is active High.
The CR10 Configuration Register bit becomes “don't care” if
CR4 is set to ‘1’, in which case the READY_WAIT pin
behaves like a READY pin (default value).
READY_WAIT Bit (CR4)
The READY_WAIT Configuration Register bit is a user-
configurable bit. The default value is ‘1’, where the
READY_WAIT signal is configured as an input with the
Ready function (CR4 = '1'). This particular configuration
allows the use of the READY_WAIT signal for handshaking
during the configuration sequence and during a Reset (RP)
pulse as the device holds the pin Low until the entire internal
configuration of the device finishes. With CR4 = 1, the
external pin can also be used by the end user to retrigger the
first address latching sequence (FALS), simply by applying a
High, a Low, and then a High pulse on the READY_WAIT
pin. See "First Address Latching Sequence," page 41.
Data Output Configuration Bit (CR9)
The Data Output Configuration bit is used to configure the
output to remain valid for either one or two clock cycles
during synchronous mode. When this bit is ‘0’, the output
data is valid for one clock cycle; when the bit is ‘1’, the
output data is valid for two clock cycles.
The Data Output Configuration must be configured using
the following condition:
t > t
+ t
QVK_CPU
K
KQV
When CR4 = '0', the READY_WAIT signal assumes the
standard WAIT functionality.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
25
XILINX [ XILINX, INC ]
