R
Functional Description
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
The Persist option will maintain A20-A23 as configuration
pins although they are not used in SelectMAP mode.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
The Slave Parallel mode is also used with BPI mode to cre-
ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure 59.
Table 65: Slave Parallel Mode Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
User I/O
HSWAP
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
Drive at valid logic level
throughout configuration.
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
D[7:0]
Input
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 1, M1 = 1, M0 = 0 Sampled User I/O
when INIT_B goes High.
Data Input.
Byte-wide data provided by host. User I/O. If bitstream
FPGA captures data on rising
CCLK edge.
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
BUSY
Output
Busy Indicator.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
User I/O. If bitstream
option Persist=Yes,
High, indicates that the FPGA is becomes part of
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
SelectMap parallel
peripheral interface.
CSI_B
Input
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
RDWR_B
CCLK
Read/Write Control. Active Low
write enable.
Must be Low throughout
configuration.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
Input
Configuration Clock. If CCLK PCB External clock.
trace is long or has multiple
connections, terminate this output to
maintain signal integrity. See CCLK
Design Considerations.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
User I/O
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
96
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DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
