Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 74: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Speed Grade
-3 -2
Symbol
Description
Device
Units
-4
-1L
Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics, page 19.
TPSDCMPLL_0
/
No Delay Global Clock and IFF(2) with DCM XC6SLX4
in Source-Synchronous Mode and PLL in
N/A
N/A
N/A
N/A
1.11/
1.38
1.21/
1.38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHDCMPLL_0
DCM2PLL Mode.
XC6SLX9
1.10/
1.38
1.20/
1.39
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
0.83/
1.12
0.83/
1.21
0.76/
1.11
0.84/
1.18
0.84/
1.02
0.84/
1.11
0.84/
1.18
N/A
N/A
N/A
N/A
N/A
N/A
0.65/
1.04
0.71/
1.12
0.68/
1.00
0.68/
1.04
0.71/
1.12
N/A
0.88/
1.06
0.94/
1.14
0.89/
1.03
0.89/
1.06
0.94/
1.14
N/A
0.56/
1.10
0.61/
1.17
0.63/
1.10
0.63/
1.10
0.63/
1.17
N/A
0.47/
1.28
0.53/
1.28
0.50/
1.28
0.50/
1.28
0.52/
1.28
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM.
These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these
measurements.
2. IFF = Input Flip-Flop
DS162 (v1.9) August 23, 2010
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