Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Spartan-6 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 75: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
TDCD_CLK
Description
Device(1)
Units
-4
-3
-2
-1L
Global Clock Tree Duty Cycle Distortion(2) LX Family
LXT Family
N/A
0.20
N/A
N/A
N/A
N/A
0.26
N/A
0.20
N/A
0.56
N/A
0.22
N/A
0.39
N/A
0.25
N/A
0.06
0.20
0.20
0.16
0.16
0.15
0.26
0.26
0.20
0.20
0.56
0.56
0.22
0.22
0.48
0.48
0.25
0.25
0.06
0.06
0.20
0.20
0.16
0.16
0.15
0.26
0.26
0.20
0.20
0.56
0.56
0.22
0.22
0.48
0.48
0.25
0.25
0.06
0.06
ns
N/A
TCKSKEW
Global Clock Tree Skew(3)
XC6SLX4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
LX Family
N/A
N/A
N/A
N/A
N/A
N/A
N/A
TDCD_BUFIO2
I/O clock tree duty cycle distortion
LXT Family
LX Family
TBUFIOSKEW
I/O clock tree skew across one clock
region
ns
ns
LXT Family
Notes:
1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade.
2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where
other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
3. The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists
CKSKEW
for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
DS162 (v1.9) August 23, 2010
www.xilinx.com
Advance Product Specification
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