R
Platform Flash In-System Programmable Configuration PROMs
XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source
X-Ref Target - Figure 8
CE
T
HCE
T
HOE
OE/RESET
CLK
T
LC
CYCO
T
T
HC
T
CLKO
CLKOUT
T
CECC
T
T
HB
SB
T
CCDD
T
DDC
T
OECC
T
CECF
T
COH
BUSY
T
OE
T
OECF
(optional)
T
CE
DATA
T
CF
T
EOH
T
CFCC
T
DF
THCF
CF
EN_EXT_SEL
REV_SEL[1:0]
T
T
T
T
HXT
SXT
HXT
SXT
T
T
T
T
HRV
SRV
HRV
SRV
Note:Typically, 8 CLKOUT cycles are output after CE rising edge, before CLKOUT
tristates, if OE/RESET remains high, and terminal count has not been reached.
ds123_25_110707
XCF08P, XCF16P,
XCF32P
Symbol
Description
Units
Min
Max
CF hold time to guarantee design revision selection is sampled
when VCCO = 3.3V or 2.5V(11)
300
300
300
THCF
CF hold time to guarantee design revision selection is sampled
when VCCO = 1.8V(11)
300
CF to data delay when VCCO = 3.3V or 2.5V
CF to data delay when VCCO = 1.8V
–
–
–
–
–
–
5
5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCF
OE/RESET to data delay(6) when VCCO = 3.3V or 2.5V
OE/RESET to data delay(6) when VCCO = 1.8V
CE to data delay(5) when VCCO = 3.3V or 2.5V
CE to data delay(5) when VCCO = 1.8V
25
25
25
25
–
TOE
TCE
Data hold from CE, OE/RESET, or CF when VCCO = 3.3V or 2.5V
Data hold from CE, OE/RESET, or CF when VCCO = 1.8V
TEOH
–
CE or OE/RESET to data float delay(2) when VCCO = 3.3V or 2.5V
CE or OE/RESET to data float delay(2) when VCCO = 1.8V
OE/RESET to CLKOUT float delay(2) when VCCO = 3.3V or 2.5V
OE/RESET to CLKOUT float delay(2) when VCCO = 1.8V
CE to CLKOUT float delay(2) when VCCO = 3.3V or 2.5V
CE to CLKOUT float delay(2) when VCCO = 1.8V
45
45
TDF
TOECF
TCECF
DS123 (v2.18) May 19, 2010
www.xilinx.com
Product Specification
18
XILINX [ XILINX, INC ]
