R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max
Units
Sequential Delays
TSHCKO16
TSHCKO32
Clock CLK to X/Y outputs (WE active, 16 x 1 mode)
Clock CLK to X/Y outputs (WE active, 32 x 1 mode)
0.6
0.8
1.5
1.9
0.6
0.8
1.7
2.1
ns
ns
Setup/Hold Times with Respect to Clock CLK
TAS / TAH
TDS / TDH
F/G address inputs
0.42 / 0
0.53 / 0
0.7 / 0
-
-
-
0.5 / 0
0.6 / 0
0.8 / 0
-
-
-
ns
ns
ns
BX/BY data inputs (DIN)
TWS / TWH CE input (WS)
Clock CLK
TWPH
TWPL
TWC
Pulse width, High
2.1
2.1
4.2
-
-
-
2.4
2.4
4.8
-
-
-
ns
ns
ns
Pulse width, Low
Clock period to meet address write cycle time
CLB Shift Register Switching Characteristics
Speed Grade
-7
-6
Symbol
Sequential Delays
TREG
Description
Min
Max
Min
Max
Units
Clock CLK to X/Y outputs
1.2
2.9
1.2
3.2
ns
Setup/Hold Times with Respect to Clock CLK
TSHDICK
TSHCECK
Clock CLK
TSRPH
BX/BY data inputs (DIN)
CE input (WS)
0.53 / 0
0.7 / 0
-
-
0.6 / 0
0.8 / 0
-
-
ns
ns
Pulse width, High
Pulse width, Low
2.1
2.1
-
-
2.4
2.4
-
-
ns
ns
TSRPL
Block RAM Switching Characteristics
Speed Grade
-7
-6
Symbol
Sequential Delays
TBCKO
Description
Clock CLK to DOUT output
Min
Max
Min
Max
Units
0.6
3.1
0.6
3.5
ns
Setup/Hold Times with Respect to Clock CLK
TBACK / TBCKA
TBDCK/ TBCKD
TBECK/ TBCKE
TBRCK/ TBCKR
TBWCK/ TBCKW
Clock CLK
TBPWH
ADDR inputs
DIN inputs
EN inputs
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
-
-
-
-
-
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
-
-
-
-
-
ns
ns
ns
ns
ns
RST input
WEN input
Pulse width, High
1.4
1.4
2.7
-
-
-
1.5
1.5
3.0
-
-
-
ns
ns
ns
TBPWL
Pulse width, Low
TBCCS
CLKA -> CLKB setup time for different ports
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
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Product Specification
XILINX [ XILINX, INC ]
