R
Spartan-IIE FPGA Family: DC and Switching Characteristics
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max Units
Combinatorial Delays
TILO
TIF5
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
0.18
0.3
0.3
0.3
0.04
-
0.42
0.8
0.8
0.9
0.2
0.7
0.18
0.3
0.3
0.3
0.04
-
0.47
0.9
ns
ns
ns
ns
ns
ns
TIF5X
0.9
TIF6Y
1.0
TF5INY
TIFNCTL
0.22
0.8
Incremental delay routing through transparent latch to
XQ/YQ outputs
TBYYB
Sequential Delays
TCKO
BY input to YB output
0.18
0.46
0.18
0.51
ns
FF clock CLK to XQ/YQ outputs
Latch clock CLK to XQ/YQ outputs
0.3
0.3
0.9
0.9
0.3
0.3
1.0
1.0
ns
ns
TCKLO
Setup/Hold Times with Respect to Clock CLK
TICK / TCKI 4-input function: F/G inputs
1.0 / 0
1.4 / 0
0.8 / 0
1.5 / 0
0.7 / 0
0.7 / 0
-
-
-
-
-
-
-
1.1 / 0
1.5 / 0
0.8 / 0
1.6 / 0
0.8 / 0
0.7 / 0
0.6 / 0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
TIF5CK / TCKIF5 5-input function: F/G inputs
TF5INCK / TCKF5IN 6-input function: F5IN input
TIF6CK / TCKIF6 6-input function: F/G inputs via F6 MUX
TDICK / TCKDI
BX/BY inputs
TCECK / TCKCE CE input
TRCK / TCKR
Clock CLK
TCH
SR/BY inputs (synchronous)
0.52 / 0
Pulse width, High
Pulse width, Low
1.3
1.3
-
-
1.4
1.4
-
-
ns
ns
TCL
Set/Reset
TRPW
Pulse width, SR/BY inputs
2.1
0.3
-
2.4
0.3
-
ns
ns
TRQ
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
0.9
1.0
FTOG
Toggle frequency (for export control)
-
400
-
357
MHz
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
45
Product Specification
XILINX [ XILINX, INC ]
