R
Spartan-IIE FPGA Family: DC and Switching Characteristics
TBUF Switching Characteristics
Speed Grade
-7
-6
Symbol
TIO
Description
Max
0
Max
0
Units
ns
IN input to OUT output
TOFF
TON
TRI input to OUT output high impedance
TRI input to valid data on OUT output
0.1
0.1
0.11
0.11
ns
ns
JTAG Test Access Port Switching Characteristics
Speed Grade
-7
-6
Symbol
Description
Min
Max
Min
Max
Units
Setup/Hold Times with Respect to TCK
TTAPTCK / TTCKTAP TMS and TDI setup times and hold times
Sequential Delays
4.0 / 2.0
-
4.0 / 2.0
-
ns
TTCKTDO
Output delay from clock TCK to output TDO
TCK clock frequency
-
-
11.0
33
-
-
11.0
33
ns
MHz
FTCK
Configuration Switching Characteristics
(1)
V
T
POR
CC
PROGRAM
INIT
T
PL
T
ICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
DS001_12_102301
.
All Devices
Symbol
TPOR
Description
Min
Max
2
Units
ms
Power-on reset
Program latency
-
-
TPL
100
4
μs
TICCK
CCLK output delay (Master serial
mode only)
0.5
μs
TPROGRAM Program pulse width
300
-
ns
Notes:
1. Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recommended operating voltage.
Figure 23: Configuration Timing on Power-Up
48
www.xilinx.com
DS077-3 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
