R
Spartan-IIE FPGA Family: DC and Switching Characteristics
DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
worst-case values across the recommended operating con-
ditions.
Speed Grade
-7
-6
Symbol
FCLKINHF
FCLKINLF
TDLLPW
Description
FCLKIN
-
Min
60
Max
Min
60
Max
Units
MHz
MHz
ns
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width
320
275
-
25
160
25
135
≥25 MHz
≥50 MHz
≥100 MHz
≥150 MHz
≥200 MHz
≥250 MHz
≥300 MHz
5.0
3.0
2.4
2.0
1.8
1.5
1.3
-
-
-
-
-
-
-
5.0
3.0
2.4
2.0
1.8
1.5
NA
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 22, page 44, provides definitions for various parame-
ters in the table below.
CLKDLLHF
CLKDLL
Min Max
Symbol
TIPTOL
TIJITCC
TLOCK
Description
FCLKIN
Min
Max
1.0
150
20
-
Units
ns
Input clock period tolerance
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.0
300
20
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock(1)
ps
> 60 MHz
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
μs
μs
μs
μs
μs
ps
25
-
50
-
90
-
120
60
TOJITCC
TPHIO
TPHOO
TPHIOM
Output jitter (cycle-to-cycle) for any DLL clock output(2)
Phase offset between CLKIN and CLKO(3)
Phase offset between clock outputs on the DLL(4)
Phase difference between CLKIN and CLKO(5)
60
100
140
160
200
100
140
160
200
ps
ps
ps
TPHOOM Phase difference between clock outputs on the DLL(6)
Notes:
1. Commercial operating conditions. Add 30% for Industrial operating conditions.
2. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
ps
3. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
4. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
5. Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
6. Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
43
Product Specification
XILINX [ XILINX, INC ]
