R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Clock Distribution Switching Characteristics
TGPIO is specified for LVTTL levels. For other standards, adjust TGPIO with the values shown in I/O Standard Global Clock
Input Adjustments.
Speed Grade
-7
-6
Symbol
Description
Max
Max
Units
GCLK IOB and Buffer
TGPIO
TGIO
Global clock pad to output
0.7
0.7
0.5
ns
ns
Global clock buffer I input to O output
0.45
I/O Standard Global Clock Input Adjustments
Delays associated with a global clock input pad are specified for LVTTL levels. For other standards, adjust the delays by the
values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Data Input Delay Adjustments
TGPLVTTL
TGPLVCMOS2
TGPLVCMOS18
TGPLVCDS
TGPLVPECL
TGPPCI33_3
TGPPCI66_3
TGPGTL
Standard-specific global clock
input delay adjustments
LVTTL
LVCMOS2
LVCMOS18
LVDS
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0.2
0.2
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
0.38
0.38
0.08
–0.11
0.37
0.37
0.27
0.27
0.27
0.33
0.27
LVCPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
TGPGTLP
GTL+
TGPHSTL
HSTL
TGPSSTL2
TGPSSTL3
TGPCTT
SSTL2
SSTL3
CTT
TGPAGP
AGP
Notes:
1. Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
42
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DS077-3 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
