R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Virtex-II Performance Characteristics
This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II devices. The numbers reported here are worst-case
values; they have all been fully characterized. Note that
these values are subject to the same guidelines as Virtex-II
Switching Characteristics, page 9 (speed files).
Table 11 provides pin-to-pin values (in nanoseconds)
including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.
Table 11: Pin-to-Pin Performance
Description
Basic Functions
Device Used & Speed Grade Pin-to-Pin (with I/O delays) Units
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
6.3
7.7
9.3
5.7
6.5
6.7
8.7
5.0
ns
ns
ns
ns
ns
ns
ns
ns
8:1 MUX
16:1 MUX
32:1 MUX
Combinatorial (pad to LUT to pad)
Memory
Block RAM
1.6
9.5
ns
ns
Pad to setup
Clock to Pad
Distributed RAM
Pad to setup
XC2V1000 -5
XC2V1000 -5
2.7
ns
ns
5.1 (no clk skew)
Clock to Pad
Table 12 shows internal (register-to-register) performance. Values are reported in MHz.
Table 12: Register-to-Register Performance
Device Used & Speed
Grade
Register-to-Register
Performance
Description
Basic Functions
Units
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
398
291
274
563
454
414
323
613
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Register to LUT to Register
DS031-3 (v3.5) November 5, 2007
Product Specification
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