R
Virtex-II Platform FPGAs: Pinout Information
Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000
Bank
Pin Description
Pin Number No Connect in XC2V1500 No Connect in XC2V2000
2
IO_L96P_2
N23
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
N26
P26
P23
P22
P19
N19
P21
P20
IO_L94N_3
IO_L94P_3
IO_L93N_3/VREF_3
IO_L93P_3
IO_L91N_3
IO_L91P_3
IO_L78N_3
IO_L78P_3
R26
R25
R20
R19
R24
R23
R22
R21
T26
T25
T20
T19
T24
T23
T22
T21
U26
V26
U24
U23
U22
U21
V25
V24
V23
V22
W26
NC
NC
NC
NC
NC
NC
NC
NC
IO_L76N_3
IO_L76P_3
IO_L75N_3/VREF_3
IO_L75P_3
IO_L73N_3
IO_L73P_3
IO_L72N_3
IO_L72P_3
IO_L70N_3
IO_L70P_3
IO_L69N_3/VREF_3
IO_L69P_3
IO_L67N_3
IO_L67P_3
IO_L54N_3
IO_L54P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
IO_L46N_3
DS031-4 (v3.5) November 5, 2007
Product Specification
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