R
Virtex-II Platform FPGAs: Pinout Information
Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000
Bank
6
Pin Description
IO_L46P_6
Pin Number
R2
No Connect in XC2V250
No Connect in XC2V500
6
IO_L46N_6
IO_L48P_6
R1
6
P6
6
IO_L48N_6
IO_L49P_6
P5
6
P4
NC
NC
NC
NC
NC
NC
NC
NC
6
IO_L49N_6
IO_L51P_6
P3
6
P2
6
IO_L51N_6/VREF_6
IO_L52P_6
P1
6
N6
6
IO_L52N_6
IO_L54P_6
N5
6
N4
6
IO_L54N_6
IO_L91P_6
N3
6
N2
6
IO_L91N_6
IO_L93P_6
N1
6
M6
M5
M4
M3
M2
M1
6
IO_L93N_6/VREF_6
IO_L94P_6
6
6
IO_L94N_6
IO_L96P_6
6
6
IO_L96N_6
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
L2
L3
L4
L5
K1
K2
K3
K4
L6
K6
K5
J5
J1
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
IO_L91P_7
IO_L91N_7
IO_L54P_7
NC
NC
NC
NC
NC
IO_L54N_7
IO_L52P_7
IO_L52N_7
IO_L51P_7/VREF_7
DS031-4 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 4 of 4
27
XILINX [ XILINX, INC ]
