R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Write Operation
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Read
Operation
Address read cycle time
Data Valid after address change (no Write Enable)
Address setup time before clock K
Speed Grade
Size
Symbol
Min
-3
Max
Min
-1
Units
Max
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
9.0
9.0
4.5
4.5
2.2
2.2
0
0
2.0
2.5
0
0
2.0
1.8
0
0
6.8
8.1
7.7
7.7
3.9
3.9
1.7
1.7
0
0
1.7
2.1
0
0
1.6
1.5
0
0
5.8
6.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16x2
32x1
16x2
32x1
16x2
32x1
T
RC
T
RCT
T
ILO
T
IHO
T
ICK
T
IHCK
4.5
6.5
1.6
2.7
1.3
2.3
2.6
3.8
1.3
2.2
0.9
1.7
ns
ns
ns
ns
ns
ns
6
DS029 (v1.2) February 9, 2000
XILINX [ XILINX, INC ]
