R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Speed Grade
Device
-3
-1
Units
Description
Symbol
Max
Max
From pad through Global Low Skew buffer, to any clock K
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
3.6
4.8
6.3
-
-
-
-
ns
ns
ns
ns
GLS
5.7
From pad through Global Early buffer, to any IOB clock. Values are for
BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and
for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
2.4
3.1
4.9
-
-
-
-
ns
ns
ns
ns
GE
4.7
4
DS029 (v1.2) February 9, 2000
XILINX [ XILINX, INC ]
