R
XC3000 Series Field Programmable Gate Arrays
RESET Timing
but with incorrect configuration and the possibility of inter-
nal contention.
As with DONE timing, the timing of the release of the inter-
nal reset can be controlled to occur either a CCLK cycle
before, or after, the outputs going active. See Figure 22.
This reset keeps all user programmable flip-flops and
latches in a zero state during configuration.
An XC3000A/XC3100A/XC3000L/XC3100L device starts
any new frame only if the three preceding bits are all ones.
If this check fails, it pulls INIT Low and stops the internal
configuration, although the Master CCLK keeps running.
The user must then start a new configuration by applying a
>6 µs Low level on RESET.
Crystal Oscillator Division
A selection allows the user to incorporate a dedicated
divide-by-two flip-flop between the crystal oscillator and the
alternate clock line. This guarantees a symmetrical clock
signal. Although the frequency stability of a crystal oscilla-
tor is very good, the symmetry of its waveform can be
affected by bias or feedback drive.
This simple check does not protect against random bit
errors, but it offers almost 100 percent protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, or PC-board level defects, such as bro-
ken lines or solder-bridges.
Bitstream Error Checking
Reset Spike Protection
Bitstream error checking protects against erroneous con-
figuration.
A separate modification slows down the RESET input
before configuration by using a two-stage shift register
driven from the internal clock. It tolerates submicrosecond
High spikes on RESET before configuration. The XC3000
master can be connected like an XC4000 master, but with
its RESET input used instead of INIT. (On XC3000, INIT is
output only).
Each Xilinx FPGA bitstream consists of a 40-bit preamble,
followed by a device-specific number of data frames. The
number of bits per frame is also device-specific; however,
each frame ends with three stop bits (111) followed by a
start bit for the next frame (0).
All devices in all XC3000 families start reading in a new
frame when they find the first 0 after the end of the previous
frame. An original XC3000 device does not check for the
correct stop bits, but XC3000A, XC3100A, XC3000L, and
XC3100L devices check that the last three bits of any frame
are actually 111.
Soft Start-up
After configuration, the outputs of all FPGAs in a
daisy-chain become active simultaneously, as a result of
the same CCLK edge. In the original XC3000/3100
devices, each output becomes active in either fast or
slew-rate limited mode, depending on the way it is config-
ured. This can lead to large ground-bounce signals. In
XC3000A, XC3000L, XC3100A, and XC3100L devices, all
outputs become active first in slew-rate limited mode,
reducing the ground bounce. After this soft start-up, each
individual output slew rate is again controlled by the
respective configuration bit.
Under normal circumstances, all these FPGAs behave the
same way; however, if the bitstream is corrupted, an
XC3000 device will always start a new frame as soon as it
finds the first 0 after the end of the previous frame, even if
the data is completely wrong or out-of-sync. Given suffi-
cient zeros in the data stream, the device will also go Done,
7-24
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
