R
XC3000 Series Field Programmable Gate Arrays
A re-program is initiated.when a configured XC3000 series
device senses a High-to-Low transition and subsequent >6
µs Low level on the DONE/PROG package pin, or, if this
pin is externally held permanently Low, a High-to-Low tran-
sition and subsequent >6 µs Low time on the RESET pack-
age pin.
generated by the development system begins with a pre-
amble of 111111110010 followed by a 24-bit length count
representing the total number of configuration clocks
needed to complete loading of the configuration pro-
gram(s). The data framing is shown in Figure 21. All
FPGAs connected in series read and shift preamble and
length count in on positive and out on negative configura-
tion clock edges. A device which has received the pream-
ble and length count then presents a High Data Out until it
has intercepted the appropriate number of data frames.
When the configuration program memory of an FPGA is full
and the length count does not yet compare, the device
shifts any additional data through, as it did for preamble
and length count. When the FPGA configuration memory is
full and the length count compares, the device will execute
The device returns to the Clear state where the configura-
tion memory is cleared and mode lines re-sampled, as for
an aborted configuration. The complete configuration pro-
gram is cleared and loaded during each configuration pro-
gram cycle.
Length count control allows a system of multiple Field Pro-
grammable Gate Arrays, of assorted sizes, to begin opera-
tion in a synchronized fashion. The configuration program
11111111
—Dummy Bits*
0010
—Preamble Code
Header
< 24-Bit Length Count >
1111
—Configuration Program Length
—Dummy Bits (4 Bits Minimum)
0 <Data Frame # 001 > 111
0 <Data Frame # 002 > 111
0 <Data Frame # 003 > 111
For XC3120
.
.
.
.
.
.
.
.
.
197 Configuration Data Frames
Program Data
(Each Frame Consists of:
A Start Bit (0)
Repeated for Each Logic
Cell Array in a Daisy Chain
0 <Data Frame # 196 > 111
0 <Data Frame # 197 > 111
A 71-Bit Data Field
Three Stop Bits
1111
Postamble Code (4 Bits Minimum)
*The LCA Device Require Four Dummy Bits Min; Software Generates Eight Dummy Bits
X5300_01
XC3042A
XC3090A
XC3090L
XC3190A
XC3190L
XC3020A
XC3020L
XC3120A
XC3030A
XC3030L
XC3130A
XC3042L
XC3142A
XC3142L
XC3064A
XC3064L
XC3164A
Device
XC3195A
Gates
1,000 to 1,500 1,500 to 2,000 2,000 to 3,000 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500
CLBs
64
(8 x 8)
64
100
(10 x 10)
80
144
(12 x 12)
96
224
(16 x 14)
120
320
(20 x 16)
144
484
(22 x 22)
176
Row x Col
IOBs
Flip-flops
256
16
360
480
688
928
1,320
44
Horizontal Longlines
TBUFs/Horizontal LL
20
24
32
40
9
11
13
15
17
23
Bits per Frame
75
92
108
140
172
188
(including1 start and 3 stop bits)
Frames
197
241
285
329
373
505
Program Data =
14,779
22,176
30,784
46,064
64,160
94,944
Bits x Frames + 4 bits
(excludes header)
PROM size (bits) =
Program Data
14,819
22,216
30,824
46,104
64,200
94,984
+ 40-bit Header
Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data
frames generated by the Development System.
The Length Count produced by the program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8] – (2 ≤ K ≤ 4) where K is a function of DONE and RESET timing selected. An additional 8 is
added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is
reached.
7-20
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
