R
XC3000 Series Field Programmable Gate Arrays
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
*
IF READBACK IS
+5 V
ACTIVATED, A
5-kΩ RESISTOR IS
REQUIRED IN
*
SERIES WITH M1
M0
M1 PWRDWN
TO DIN OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
DURING CONFIGURATION
THE 5 kΩ M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
DOUT
M2
TO CCLK OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
BUT IT ALLOWS M2 TO
BE USER I/O.
+5V
HDC
LDC
INIT
GENERAL-
PURPOSE
USER I/O
PINS
•
•
•
•
•
7
OTHER
I/O PINS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
XC3000
TO DIN OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
FPGA
DEVICE
+5 V
RESET
RESET
V
CC
V
PP
DIN
DATA
CLK
CE
DATA
CCLK
CLK
CE
CASCADED
SERIAL
MEMORY
SCP
D/P
INIT
CEO
OE/RESET
XC17xx
OE/RESET
(LOW RESETS THE XC17xx ADDRESS POINTER)
X5989_01
Figure 23: Master Serial Mode Circuit Diagram
November 9, 1998 (Version 3.1)
7-25
XILINX [ XILINX, INC ]
