R
XC3000 Series Field Programmable Gate Arrays
Dynamic Power Consumption
XC3042A
0.25
XC3042L
0.17
XC3142A
0.25
One CLB driving three local interconnects
One global clock buffer and clock line
One device output with a 50 pF load
mW per MHz
mW per MHz
mW per MHz
2.25
1.40
1.70
1.25
1.25
1.25
Power Consumption
The Field Programmable Gate Array exhibits the low power
consumption characteristic of CMOS ICs. For any design,
the configuration option of TTL chip input threshold
requires power for the threshold reference. The power
required by the static memory cells that hold the configura-
tion data is very low and may be maintained in a
power-down mode.
has built in powerdown logic which, when activated, will
disable normal operation of the device and retain only the
configuration data. All internal operation is suspended and
output buffers are placed in their high-impedance state with
no pull-ups. Different from the XC3000 family which can be
powered down to a current consumption of a few micro-
amps, the XC3100A draws 5 mA, even in power-down.
This makes power-down operation less meaningful. In con-
Typically, most of power dissipation is produced by external
capacitive loads on the output buffers. This load and fre-
quency dependent power is 25 µW/pF/MHz per output.
Another component of I/O power is the external dc loading
on all output pins.
trast, I
for the XC3000L is only 10 µA.
CCPD
To force the FPGA into the Powerdown state, the user must
pull the PWRDWN pin Low and continue to supply a reten-
tion voltage to the V
pins. When normal power is
CC
restored, V
is elevated to its normal operating voltage
CC
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an FPGA, the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a long
binary counter, the total activity of all counter flip-flops is
equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is
between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz
for the XC3090A. The internal capacitive load is more a
function of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
and PWRDWN is returned to a High. The FPGA resumes
operation with the same internal sequence that occurs at
the conclusion of configuration. Internal-I/O and logic-block
storage elements will be reset, the outputs will become
enabled and the DONE/PROG pin will be released.
7
When V
is shut down or disconnected, some power
CC
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input pro-
tection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and drive
the V
connection. This condition can produce invalid
CC
Because the control storage of the FPGA is CMOS static
memory, its cells require a very low standby current for data
retention. In some systems, this low data retention current
characteristic can be used as a method of preserving con-
figurations in the event of a primary power loss. The FPGA
power conditions and should be avoided. A large series
resistor might be used to limit the current or a bipolar buffer
may be used to isolate the input signal.
November 9, 1998 (Version 3.1)
7-37
XILINX [ XILINX, INC ]
