R
XC3000 Series Field Programmable Gate Arrays
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Symbol
Description
Min
4.75
4.5
2.0
0
Max
5.25
5.5
Units
Supply voltage relative to GND Commercial 0°C to +85°C junction
Supply voltage relative to GND Industrial -40°C to +100°C junction
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
High-level input voltage — CMOS configuration
Low-level input voltage — CMOS configuration
Input signal transition time
V
V
V
V
V
CC
V
V
CC
IHT
V
0.8
100%
20%
250
ILT
V
70%
0
V
V
IHC
CC
V
ILC
CC
T
ns
IN
Note:
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
XC3000A DC Characteristics Over Operating Conditions
Symbol
Description
High-level output voltage (@ I = –4.0 mA, V min)
Min
Max
0.40
0.40
Units
V
3.86
V
V
V
V
V
OH
OH
CC
Commercial
Industrial
V
Low-level output voltage (@ I = 4.0 mA, V min)
OL CC
OL
7
V
High-level output voltage (@ I = –4.0 mA, V min)
3.76
2.30
OH
OH
CC
V
Low-level output voltage (@ I = 4.0 mA, V min)
OL CC
OL
V
Power-down supply voltage (PWRDWN must be Low)
CCPD
CCPD
I
Power-down supply current
(V
@ T
)
MAX
3020A
3030A
3042A
3064A
3090A
100
160
240
340
500
µA
µA
µA
µA
µA
CC(MAX)
Quiescent FPGA supply current in addition to I
CCPD
I
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
500
10
µA
µA
CCO
I
Input Leakage Current
–10
+10
µA
IL
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
pF
C
I
IN
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
16
20
pF
pF
Pad pull-up (when selected) @ V = 0 V3
0.02
0.17
3.4
mA
mA
RIN
RLL
IN
I
Horizontal Longline pull-up (when selected) @ logic Low
Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA
device configured with a tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per VCC pin. The number of ground pins varies from the XC3020A to the XC3090A.
3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.
November 9, 1998 (Version 3.1)
7-41
XILINX [ XILINX, INC ]
