R
XC3000 Series Field Programmable Gate Arrays
Pin Functions During Configuration
Configuration Mode <M2:M1:M0>
***
**
****
208
SLAVE
SERIAL
<1:1:1>
MASTER-
SERIAL
<0:0:0>
MASTER-
HIGH
MASTER-
LOW
<1:0:0>
100
PERIPH
<1:0:1>
44
64
68
84
84
100 VQFP 132
144
160
175
176
User
Function
<1:1:0>
PLCC VQFP PLCC PLCC PGA PQFP TQFP PGA TQFP PQFP PGA TQFP PQFP
POWR
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(I)
POWER
DWN
(1)
7
17
10
12
B2
29
26
A1
1
159
B2
1
3
M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M1 (HIGH) (I) M1 (LOW) (I)
M0 (HIGH) (I) M0 (LOW) (I) M0 (HIGH) (I) M0 (LOW) (I) M0 (LOW) (I)
M2 (HIGH) (I) M2 (LOW) (I) M2 (HIGH) (I) M2 (HIGH) (I) M2 (HIGH) (I)
16
17
18
19
20
22
23
26
27
28
31
32
33
34
36
40
41
47
48
49
50
51
52
53
54
55
57
58
59
60
61
62
63
64
1
25
26
27
28
30
34
35
43
44
45
46
47
48
49
50
51
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
2
31
32
33
34
36
42
43
53
54
55
56
57
58
60
61
62
65
66
67
70
71
72
73
74
75
76
77
78
81
82
83
84
2
J2
L1
52
54
56
57
59
65
66
76
78
80
81
82
83
87
88
89
92
93
94
98
99
100
1
49
51
53
54
56
62
63
73
75
77
78
79
80
84
85
86
89
90
91
95
96
97
98
99
2
B13
A14
C13
B14
D14
G14
H12
M13
P14
N13
M12
P13
N11
M9
N9
36
38
40
42
B14
B15
C15
E14
D16
H15
J14
P15
R15
R14
N13
T14
P12
T11
R10
R9
45
47
48
50
RDATA
RTRIG (I)
I/O
K2
40
44
49
56
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH)
HDC (HIGH)
LDC (LOW)
INIT*
K3
41
45
50
57
I/O
LDC (LOW)
INIT*
LDC (LOW)
INIT*
LDC (LOW)
INIT*
LDC (LOW)
INIT*
L3
45
49
54
61
I/O
K6
53
59
65
77
I/O
GND
GND
GND
GND
GND
J6
55
61
67
79
GND
L11
K10
J10
K11
J11
H10
F10
G10
G11
F11
E11
E10
D10
C11
B11
C10
A11
B10
B9
69
76
85
100
102
XTL2 OR I/O
RESET (I)
RESET (I)
DONE
RESET (I)
DONE
RESET (I)
DONE
RESET (I)
DONE
RESET (I)
DONE
71
78
87
73
80
89
107 PROGRAM (I)
DATA 7 (I)
DATA 7 (I)
DATA 7 (I)
74
81
90
109
110
115
122
123
128
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
184
185
192
193
199
200
203
204
I/O
30
75
82
91
XTL1 OR I/O
DATA 6 (I)
DATA 5 (I)
CS0 (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
78
86
96
I/O
84
92
102
103
108
112
113
118
124
125
130
131
132
135
136
140
141
146
147
150
151
156
157
164
165
169
170
173
174
I/O
85
93
I/O
DATA 4 (I)
DATA 3 (I)
CS1 (I)
DATA 4 (I)
DATA 3 (I)
DATA 4 (I)
DATA 3 (I)
N8
88
96
I/O
N7
92
102
103
106
114
115
119
120
121
124
125
128
129
132
133
136
137
141
142
147
148
151
152
155
156
P8
I/O
P6
93
R8
I/O
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
A0
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
A0
M6
M5
N4
96
R7
I/O
102
103
106
107
108
111
112
115
116
119
120
123
124
128
129
133
134
137
138
141
142
R5
I/O
P5
I/O
DIN (I)
DOUT
DIN (I)
DOUT
38
39
40
N2
R3
I/O
M3
P1
N4
I/O
CCLK (I)
CCLK (O)
CCLK (O)
WS (I)
2
R2
CCLK (I)
5
M2
N1
P2
I/O
CS2 (I)
A1
A1
2
6
3
M3
P1
I/O
A2
A2
3
A10
A9
8
5
L2
I/O
A3
A3
4
9
6
L1
N1
I/O
A15
A15
B6
12
13
14
15
17
18
19
20
23
24
25
26
9
K1
M1
L2
5
A4
A4
5
B7
10
11
12
14
15
16
17
20
21
22
26
J2
I/O
A14
A14
6
A7
H1
K2
I/O
A5
A5
7
C7
H2
K1
I/O
I/O
A13
A13
9
A6
G2
G1
F2
H2
A6
A6
10
11
12
13
14
15
16
3
3
A5
H1
I/O
A12
A12
4
4
B5
F2
I/O
A7
A7
5
5
C5
E1
E1
I/O
A11
A11
6
8
A3
D1
D1
I/O
A8
A8
7
9
A2
D2
C1
I/O
A10
A10
8
10
11
B3
B1
E3
I/O
A9
A9
9
A1
C2
C2
I/O
All Others
XC3x20A etc.
XC3x30A etc.
XC3x42A etc.
XC3x64A etc.
XC3x90A etc.
XC3195A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X**
X**
X**
X
X
X
X
X
X
X
Notes:
Generic I/O pins are not shown.
For a detailed description of the configuration modes, see page 25 through page 34.
For pinout details, see page 65 through page 76.
Represents a weak pull-up before and during configuration.
INIT is an open drain output during configuration.
*
(I)
Represents an input.
**
***
****
Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Note:
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
7-40
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
