R
XC3000 Series Field Programmable Gate Arrays
be used to drive the remaining unused routing, as that
might affect timing of user nets. Tie can be omitted for quick
breadboard iterations where a few additional milliamps of
Icc are acceptable.
Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 27 shows the peripheral mode connec-
tions. Processor write cycles are decoded from the com-
mon assertion of the active low Write Strobe (WS), and two
active low and one active high Chip Selects (CS0, CS1,
CS2). The FPGA generates a configuration clock from the
internal timing generator and serializes the parallel input
data for internal framing or for succeeding slaves on Data
Out (DOUT). A output High on READY/BUSY pin indicates
the completion of loading for each byte when the input reg-
ister is ready for a new byte. As with Master modes, Periph-
eral mode may also be used as a lead device for a
daisy-chain of slave devices.
The configuration bitstream begins with eight High pream-
ble bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the FPGA is set
to zero and begins to count the total number of configura-
tion clock cycles applied to the device. As each configura-
tion data frame is supplied to the device, it is internally
assembled into a data word, which is then loaded in parallel
into one word of the internal configuration memory array.
The configuration loading process is complete when the
current length count equals the loaded length count and the
required configuration program data frames have been
written. Internal user flip-flops are held Reset during config-
uration.
Slave Serial Mode
Slave Serial mode provides a simple interface for loading
the Field Programmable Gate Array configuration as
shown in Figure 29. Serial data is supplied in conjunction
with a synchronizing input clock. Most Slave mode applica-
tions are in daisy-chain configurations in which the data
input is driven from the previous FPGA’s data out, while the
clock is supplied by a lead device in Master or Peripheral
mode. Data may also be supplied by a processor or other
special circuits.
Two user-programmable pins are defined in the unconfig-
ured Field Programmable Gate Array. High During Config-
uration (HDC) and Low During Configuration (LDC) as well
as DONE/PROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
the length count compares, the user I/O pins become
active. Options allow timing choices of one clock earlier or
later for the timing of the end of the internal logic RESET
and the assertion of the DONE signal. The open-drain
DONE/PROG output can be AND-tied with multiple devices
and used as an active-High READY, an active-Low PROM
enable or a RESET to other portions of the system. The
state diagram of Figure 20 illustrates the configuration pro-
cess.
Daisy Chain
The development system is used to create a composite
configuration for selected FPGAs including: a preamble, a
length count for the total bitstream, multiple concatenated
data programs and a postamble plus an additional fill bit
per device in the serial chain. After loading and passing-on
the preamble and length count to a possible daisy-chain, a
lead device will load its configuration data frames while pro-
viding a High DOUT to possible down-stream devices as
shown in Figure 25. Loading continues while the lead
device has received its configuration program and the cur-
rent length count has not reached the full value. The addi-
tional data is passed through the lead device and appears
on the Data Out (DOUT) pin in serial form. The lead device
also generates the Configuration Clock (CCLK) to synchro-
nize the serial output data and data in of down-stream
FPGAs. Data is read in on DIN of slave devices by the pos-
itive edge of CCLK and shifted out the DOUT on the nega-
tive edge of CCLK. A parallel Master mode device uses its
internal timing generator to produce an internal CCLK of 8
times its EPROM address rate, while a Peripheral mode
device produces a burst of 8 CCLKs for each chip select
and write-strobe cycle. The internal timing generator con-
tinues to operate for general timing and synchronization of
inputs in all modes.
Configuration Modes
Master Mode
In Master mode, the FPGA automatically loads configura-
tion data from an external memory device. There are three
Master modes that use the internal timing source to supply
the configuration clock (CCLK) to time the incoming data.
Master Serial mode uses serial configuration data supplied
to Data-in (DIN) from a synchronous serial source such as
the Xilinx Serial Configuration PROM shown in Figure 23.
Master Parallel Low and High modes automatically use
parallel data supplied to the D0–D7 pins in response to the
16-bit address generated by the FPGA. Figure 25 shows
an example of the parallel Master mode connections
required. The HEX starting address is 0000 and increments
for Master Low mode and it is FFFF and decrements for
Master High mode. These two modes provide address
compatibility with microprocessors which begin execution
from opposite ends of memory.
7-22
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
