R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 8: Supported Sources for XC4000 Series Device
Inputs
Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
XC4000E/EX XC4000XL
Series Inputs Series Inputs
Source
5 V,
5 V,
3.3 V
TTL CMOS
CMOS
Any device, Vcc = 3.3 V,
CMOS outputs
√
√
√
√
√
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
IOB (not at the clock pin). Any routing delay from the device
clock pin to the clock input of the IOB must, therefore, be
subtracted from this setup time to arrive at the real setup
time requirement relative to the device pins. A short speci-
fied setup time might, therefore, result in a negative setup
time at the device pins, i.e., a positive hold-time require-
ment.
Unreli
-able
Data
XC4000 Series, Vcc = 5 V,
TTL outputs
√
√
√
Any device, Vcc = 5 V,
TTL outputs (Voh ≤ 3.7 V)
Any device, Vcc = 5 V,
CMOS outputs
√
XC4000XL 5-Volt Tolerant I/Os
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the default.
The I/Os on the XC4000XL are fully 5-volt tolerant even
though the VCC is 3.3 volts. This allows 5 V signals to
directly connect to the XC4000XL inputs without damage,
as shown in Table 8. In addition, the 3.3 volt VCC can be
applied before or after 5 volt signals are applied to the I/Os.
This makes the XC4000XL immune to power supply
sequencing problems.
The XC4000E IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See “Global Nets and
Buffers (XC4000E only)” on page 35 for a description of the
global clock buffers in the XC4000E.) For a shorter input
register setup time, with non-zero hold, attach a NODELAY
attribute or property to the flip-flop.
Registered Inputs
The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each IOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000 Series CLB. It cannot be inverted within the
IOB.
The XC4000X IOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired delay are
shown in Table 10. The choices are no added attribute,
MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000X clock buffers, including the Global Low-Skew
buffers. MEDDELAY ensures no hold time with respect to
the Global Early buffers. Inputs with NODELAY may have a
positive hold time with respect to all clock buffers. For a
description of each of these buffers, see “Global Nets and
Buffers (XC4000X only)” on page 37.
The storage element behavior is shown in Table 9.
Table 9: Input Register Functionality
(active rising edge is shown)
Clock
Enable
Mode
Clock
D
Q
Power-Up or
GSR
X
X
X
SR
Table 10: XC4000X IOB Input Delay Element
Flip-Flop
__/
0
1*
X
D
X
X
D
X
D
Q
Q
D
Q
Value
full delay
When to Use
Latch
1
1*
1*
0
Zero Hold with respect to Global
0
(default, no
Low-Skew Buffer, Global Early Buffer
attribute added)
Both
X
Legend:
MEDDELAY
Zero Hold with respect to Global Early
Buffer
X
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
__/
SR
0*
NODELAY
Short Setup, positive Hold time
1*
6-22
May 14, 1999 (Version 1.6)
XILINX [ XILINX, INC ]
