X24C01
Sequential Read
Thedataoutputissequential,withthedatafromaddress
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
oneoperation. Attheendoftheaddressspace(address
127) the counter “rolls over” to zero and the X24C01
continues to output data for each acknowledge re-
ceived. Refer to Figure 8 for the address, acknowledge
and data transfer sequence.
Sequential read is initiated in the same manner as the
byte read. The first data byte is transmitted as with the
byte read mode, however, the master now responds
with an acknowledge, indicating it requires additional
data. The X24C01 continues to output data for each
acknowledge received. The read operation is termi-
natedbythemaster;bynotrespondingwithanacknowl-
edge and by issuing a stop condition.
Figure 8. Sequential Read
S
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY: ADDRESS
SDA LINE
P
R A
/
W
BUS ACTIVITY:
X24C01
C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
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Figure 9. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
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7
XICOR [ XICOR INC. ]
