X24C01
Acknowledge Polling
Figure 6. ACK Polling Sequence
The disabling of the inputs can be used to take advan-
tage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation the X24C01 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the word address
for a write operation. If the X24C01 is still busy with the
write operation no ACK will be returned. If the X24C01
has completed the write operation an ACK will be
returned and the controller can then proceed with the
next read or write operation.
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ISSUE STOP
ADDRESS AND R/W = 0
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with exception that the R/W bit of the
word address is set to a one. There are two basic read
operations: byte read and sequential read.
ACK
NO
RETURNED?
YES
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
duringtheninthcycleorholdSDAHIGHduringtheninth
clock cycle and then issue a stop condition.
NEXT
NO
OPERATION
A WRITE?
YES
ISSUE STOP
PROCEED
Byte Read
To initiate a read operation, the master sends a start
condition followed by a seven bit word address and a
read bit. The X24C01 responds with an acknowledge
and then transmits the eight bits of data. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
Refer to Figure 7 for the start, word address, read bit,
acknowledge and data transfer sequence.
PROCEED
3837 FHD F11
Figure 7. Byte Read
S
T
A
R
T
S
T
O
P
WORD
ADDRESS n
BUS ACTIVITY:
MASTER
SDA LINE
S
P
M
S
B
L R A
/
W
BUS ACTIVITY:
X24C01
S
B
C
K
DATA n
3837 FHD F12
6
XICOR [ XICOR INC. ]
