X24C01
WRITE OPERATIONS
Byte Write
the page address. The X24C01 is capable of a four byte
page write operation. It is initiated in the same manner as
the byte write operation, but instead of terminating the
transfer of data after the first data byte, the master can
transmit up to three more bytes. After the receipt of each
data byte, the X24C01 will respond with an acknowledge.
To initiate a write operation, the master sends a start
conditionfollowedbyasevenbitwordaddressandawrite
bit. The X24C01 responds with an acknowledge, then
waits for eight bits of data and then responds with an
acknowledge. The master then terminates the transfer by
generating a stop condition, at which time the X24C01
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress, the X24C01
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 4 for the
address, acknowledge and data transfer sequence.
After the receipt of each data byte, the two low order
addressbitsareinternallyincrementedbyone. Thehigh
order five bits of the address remain constant. If the
master should transmit more than four data bytes prior
togeneratingthestopcondition,theaddresscounterwill
“roll over” and the previously transmitted data will be
overwritten. As with the byte write operation, all inputs
are disabled until completion of the internal write cycle.
RefertoFigure5fortheaddress, acknowledgeanddata
transfer sequence.
Page Write
The most significant five bits of the word address define
Figure 4. Byte Write
S
T
A
R
T
S
WORD
ADDRESS (n)
BUS ACTIVITY:
SDA LINE
T
O
P
DATA n
S
P
M
S
B
L R A
/
W
A
C
K
BUS ACTIVITY:
X24C01
S
B
C
K
3837 FHD F09
Figure 5. Page Write
S
T
A
R
T
S
T
WORD
ADDRESS (n)
BUS ACTIVITY:
SDA LINE
DATA n
DATA n+1
DATA n+3
O
P
S
P
M
S
B
L R A
/
W
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C01
S
B
C
K
3837 FHD F10
5
XICOR [ XICOR INC. ]
