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X1227S8I-2.7 参数 Datasheet PDF下载

X1227S8I-2.7图片预览
型号: X1227S8I-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历/ CPU监控器, EEPROM [Real Time Clock/Calendar/CPU Supervisor with EEPROM]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 28 页 / 442 K
品牌: XICOR [ XICOR INC. ]
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X1227  
Figure 6. Reset V  
Level Sequence  
TRIP  
V
= 15V  
P
RESET  
V
V
CC  
CC  
0
1 2 3 4 5 6 7  
0
1
2 3  
4
5 6  
7
0
1
2 3  
4
5 6  
7
0
1
2 3  
4
5 6 7  
SCL  
SDA  
AEh  
00h  
03h  
00h  
Note: BP0, BP1, BP2 must be disabled.  
SERIAL COMMUNICATION  
Interface Conventions  
Acknowledge  
Acknowledge is a software convention used to indicate  
successful data transfer. The transmitting device, either  
master or slave, will release the bus after transmitting  
eight bits. During the ninth clock cycle, the receiver will  
pull the SDA line LOW to acknowledge that it received  
the eight bits of data. Refer to Figure 9.  
The device supports a bidirectional bus oriented proto-  
col. The protocol defines any device that sends data  
onto the bus as a transmitter, and the receiving device  
as the receiver. The device controlling the transfer is  
called the master and the device being controlled is  
called the slave.The master always initiates data trans-  
fers, and provides the clock for both transmit and  
receive operations. Therefore, the devices in this family  
operate as slaves in all applications.  
The device will respond with an acknowledge after rec-  
ognition of a start condition and if the correct Device  
Identifier and Select bits are contained in the Slave  
Address Byte. If a write operation is selected, the  
device will respond with an acknowledge after the  
receipt of each subsequent eight bit word. The device  
will acknowledge all incoming data and address bytes,  
except for:  
Clock and Data  
Data states on the SDA line can change only during  
SCL LOW. SDA state changes during SCL HIGH are  
reserved for indicating start and stop conditions. See  
Figure 7.  
– The Slave Address Byte when the Device Identifier  
and/or Select bits are incorrect  
– All Data Bytes of a write when the WEL in the Write  
Protect Register is LOW  
Start Condition  
All commands are preceded by the start condition,  
which is a HIGH to LOW transition of SDA when SCL is  
HIGH. The device continuously monitors the SDA and  
SCL lines for the start condition and will not respond to  
any command until this condition has been met. See  
Figure 8.  
– The 2nd Data Byte of a Status Register Write Opera-  
tion (only 1 data byte is allowed)  
In the read mode, the device will transmit eight bits of  
data, release the SDA line, then monitor the line for an  
acknowledge. If an acknowledge is detected and no  
stop condition is generated by the master, the device  
will continue to transmit data. The device will terminate  
further data transmissions if an acknowledge is not  
detected. The master must then issue a stop condition  
to return the device to Standby mode and place the  
device into a known state.  
Stop Condition  
All communications must be terminated by a stop  
condition, which is a LOW to HIGH transition of SDA  
when SCL is HIGH. The stop condition is also used to  
place the device into the Standby power mode after a  
read sequence. A stop condition can only be issued  
after the transmitting device has released the bus. See  
Figure 8.  
Characteristics subject to change without notice. 10 of 28  
REV 1.1.20 1/13/03  
www.xicor.com  
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