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X1227S8I-2.7 参数 Datasheet PDF下载

X1227S8I-2.7图片预览
型号: X1227S8I-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历/ CPU监控器, EEPROM [Real Time Clock/Calendar/CPU Supervisor with EEPROM]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 28 页 / 442 K
品牌: XICOR [ XICOR INC. ]
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X1227  
POWER ON RESET  
Watchdog Timer Restart  
The Watchdog Timer is started by a falling edge of  
SDA when the SCL line is high and followed by a stop  
bit. The start signal restarts the watchdog timer  
counter, resetting the period of the counter back to the  
maximum. If another start fails to be detected prior to  
the watchdog timer expiration, then the RESET pin  
becomes active. In the event that the start signal  
occurs during a reset time out period, the start will  
have no effect. When using a single START to refresh  
watchdog timer, a STOP bit should be followed to reset  
the device back to stand-by mode.  
Application of power to the X1227 activates a Power  
On Reset Circuit that pulls the RESET pin active. This  
signal provides several benefits.  
– It prevents the system microprocessor from starting  
to operate with insufficient voltage.  
– It prevents the processor from operating prior to sta-  
bilization of the oscillator.  
– It allows time for an FPGA to download its configura-  
tion prior to initialization of the circuit.  
– It prevents communication to the EEPROM, greatly  
reducing the likelihood of data corruption on power up.  
LOW VOLTAGE RESET OPERATION  
When V  
exceeds the device V  
threshold value  
CC  
TRIP  
When a power failure occurs, and the voltage to the  
for typically 250ms the circuit releases RESET, allow-  
ing the system to begin operation. Recommended slew  
rate is between 0.2V/ms and 50V/ms.  
part drops below a fixed v  
voltage, a reset pulse is  
TRIP  
issued to the host microcontroller. The circuitry moni-  
tors the V line with a voltage comparator which  
CC  
senses a preset threshold voltage. Power up and  
power down waveforms are shown in Figure 4. The  
Low Voltage Reset circuit is to be designed so the  
RESET signal is valid down to 1.0V.  
WATCHDOG TIMER OPERATION  
The watchdog timer is selectable. By writing a value to  
WD1 and WD0, the watchdog timer can be set to 3 dif-  
ferent time out periods or off. When the Watchdog  
timer is set to off, the watchdog circuit is configured for  
low power operation.  
When the low voltage reset signal is active, the operation  
of any in progress nonvolatile write cycle is unaffected,  
allowing a nonvolatile write to continue as long as possi-  
ble (down to the power on reset voltage). The low voltage  
reset signal, when active, terminates in progress commu-  
nications to the device and prevents new commands, to  
reduce the likelihood of data corruption.  
Figure ±. Watchdog Restart/Time Out  
t
t
>t  
RSP  
RSP WDO  
t
t
>t  
t
RST  
t
<t  
RST  
RSP WDO  
RSP WDO  
SCL  
SDA  
RESET  
Stop  
Start  
Start  
Note: All inputs are ignored during the active reset period (t  
).  
RST  
Characteristics subject to change without notice. 8 of 28  
REV 1.1.20 1/13/03  
www.xicor.com  
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