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X1227S8I-2.7 参数 Datasheet PDF下载

X1227S8I-2.7图片预览
型号: X1227S8I-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历/ CPU监控器, EEPROM [Real Time Clock/Calendar/CPU Supervisor with EEPROM]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 28 页 / 442 K
品牌: XICOR [ XICOR INC. ]
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X1227  
A write to a protected block of memory is ignored, but  
will still receive an acknowledge. At the end of the write  
command, the X1227 will not initiate an internal write  
cycle, and will continue to ACK commands.  
tion 40 of the memory and loads 30 bytes, then the first  
23 bytes are written to addresses 45 through 63, and  
the last 7 bytes are written to columns 0 through 6.  
Afterwards, the address counter would point to location  
7 on the page that was just written. If the master sup-  
plies more than the maximum bytes in a page, then the  
previously loaded data is over written by the new data,  
one byte at a time. Refer to Figure 12.  
Page Write  
The X1227 has a page write operation. It is initiated in  
the same manner as the byte write operation; but  
instead of terminating the write cycle after the first data  
byte is transferred, the master can transmit up to 63  
more bytes to the memory array and up to 7 more  
bytes to the clock/control registers. (Note: Prior to writ-  
ing to the CCR, the master must write a 02h, then 06h  
to the status register in two preceding operations to  
enable the write operation. See “Writing to the Clock/  
Control Registers.”  
The master terminates the Data Byte loading by issu-  
ing a stop condition, which causes the X1227 to begin  
the nonvolatile write cycle. As with the byte write oper-  
ation, all inputs are disabled until completion of the  
internal write cycle. Refer to Figure 13 for the address,  
acknowledge, and data transfer sequence.  
Stops and Write Modes  
After the receipt of each byte, the X1227 responds with  
an acknowledge, and the address is internally incre-  
mented by one. When the counter reaches the end of  
the page, it “rolls over” and goes back to the first  
address on the same page. This means that the mas-  
ter can write 64 bytes to a memory array page or 8  
bytes to a CCR section starting at any location on that  
page. For example, if the master begins writing at loca-  
Stop conditions that terminate write operations must  
be sent by the master after sending at least 1 full data  
byte and it’s associated ACK signal. If a stop is issued  
in the middle of a data byte, or before 1 full data byte +  
ACK is sent, then the X1227 resets itself without per-  
forming the write. The contents of the array are not  
affected.  
Figure 1±. Page Write Sequence  
1 n 64 for EEPROM array  
1 n 8 for CCR  
S
t
a
r
Signals from  
the Master  
S
t
o
p
Word  
Address 1  
Slave  
Address  
Word  
Address 0  
Data  
(1)  
Data  
(n)  
t
SDA Bus  
1
1 1 1 0  
0 0 0 0 0 0 0  
A
C
K
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Characteristics subject to change without notice. 13 of 28  
REV 1.1.20 1/13/03  
www.xicor.com  
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