欢迎访问ic37.com |
会员登录 免费注册
发布采购

X1227S8I-2.7 参数 Datasheet PDF下载

X1227S8I-2.7图片预览
型号: X1227S8I-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 实时时钟/日历/ CPU监控器, EEPROM [Real Time Clock/Calendar/CPU Supervisor with EEPROM]
分类和应用: 计时器或实时时钟微控制器和处理器外围集成电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 28 页 / 442 K
品牌: XICOR [ XICOR INC. ]
 浏览型号X1227S8I-2.7的Datasheet PDF文件第10页浏览型号X1227S8I-2.7的Datasheet PDF文件第11页浏览型号X1227S8I-2.7的Datasheet PDF文件第12页浏览型号X1227S8I-2.7的Datasheet PDF文件第13页浏览型号X1227S8I-2.7的Datasheet PDF文件第15页浏览型号X1227S8I-2.7的Datasheet PDF文件第16页浏览型号X1227S8I-2.7的Datasheet PDF文件第17页浏览型号X1227S8I-2.7的Datasheet PDF文件第18页  
X1227  
Acknowledge Polling  
Figure 15. Acknowledge Polling Sequence  
Disabling of the inputs during nonvolatile write cycles  
can be used to take advantage of the typical 5mS write  
cycle time. Once the stop condition is issued to indi-  
cate the end of the master’s byte load operation, the  
X1227 initiates the internal nonvolatile write cycle.  
Acknowledge polling can begin immediately. To do this,  
the master issues a start condition followed by the  
Memory Array Slave Address Byte for a write or read  
operation (AEh or AFh). If the X1227 is still busy with  
the nonvolatile write cycle then no ACK will be  
returned. When the X1227 has completed the write  
operation, an ACK is returned and the host can pro-  
ceed with the read or write operation. Refer to the flow  
chart in Figure 15. Note: Do not use the CCR slave  
byte (DEh or DFh) for acknowledge polling.  
Byte load completed  
by issuing STOP.  
Enter ACK Polling  
Issue START  
Issue Memory Array Slave  
Issue STOP  
Address Byte AFh (Read)  
or AEh (Write)  
NO  
ACK  
returned?  
YES  
Read Operations  
NO  
nonvolatile write  
Cycle complete. Continue  
command sequence?  
There are three basic read operations: Current  
Address Read, Random Read, and Sequential Read.  
Issue STOP  
Current Address Read  
YES  
Internally the X1227 contains an address counter that  
maintains the address of the last word read incre-  
mented by one. Therefore, if the last read was to  
address n, the next read operation would access data  
from address n+1. On power up, the sixteen bit  
address is initialized to 0h. In this way, a current  
address read immediately after the power on reset can  
download the entire contents of memory starting at the  
first location.Upon receipt of the Slave Address Byte  
with the R/W bit set to one, the X1227 issues an  
acknowledge, then transmits eight data bits. The mas-  
ter terminates the read operation by not responding  
with an acknowledge during the ninth clock and issuing  
a stop condition. Refer to Figure 14 for the address,  
acknowledge, and data transfer sequence.  
Continue normal  
Read or Write  
command  
sequence  
PROCEED  
It should be noted that the ninth clock cycle of the read  
operation is not a “don’t care.” To terminate a read  
operation, the master must either issue a stop condi-  
tion during the ninth cycle or hold SDA HIGH during  
the ninth clock cycle and then issue a stop condition.  
Figure 14. Current Address Read Sequence  
S
t
S
t
Signals from  
a
Slave  
Address  
o
the Master  
r
t
p
SDA Bus  
1
1 1 1 1  
A
C
K
Signals from  
the Slave  
Data  
Characteristics subject to change without notice. 14 of 28  
REV 1.1.20 1/13/03  
www.xicor.com  
 复制成功!