Pre-Production
WM8985
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
00
DESCRIPTION
REFER TO
5:4
OPCLKDIV
PLL Output clock division ratio
00=divide by 1
General
Purpose
Input/Output
(GPIO)
01=divide by 2
10=divide by 3
11=divide by 4
3
GPIO1POL
0
GPIO1 Polarity invert
0=Non inverted
General
Purpose
Input/Output
(GPIO)
1=Inverted
2:0
GPIO1SEL
[2:0]
000
CSB/GPIO1 pin function select:
General
Purpose
Input/Output
(GPIO)
000= input (CSB/jack detection: depending on
MODE setting)
001= reserved
010=Temp ok
011=Amute active
100=PLL clk o/p
101=PLL lock
110=logic 1
111=logic 0
9 (09h)
8:7
6
00
0
Reserved. Initialise to 00
JD_EN
Jack Detection Enable
0=disabled
Output
Switching
(Jack Detect)
1=enabled
5:4
JD_SEL
00
Pin selected as jack detection input
00 = GPIO1
Output
Switching
(Jack Detect)
01 = GPIO2
10 = GPIO3
11 = Reserved
3:0
8:7
6
0
Reserved. Initialise to 0
Reserved. Initialise to 0
Softmute enable:
10 (0Ah)
00
0
SOFTMUTE
Output Signal
Path
0=Disabled
1=Enabled
5:4
3
00
0
Reserved. Initialise to 0
DAC oversample rate select
0 = 64x (lowest power)
1 = 128x (best SNR)
Automute enable
DACOSR128
AMUTE
Power
Management
2
1
0
8
0
Output Signal
Path
0 = Amute disabled
1 = Amute enabled
Right DAC output polarity:
0 = non-inverted
DACPOLR
DACPOLL
DACVU
0
Output Signal
Path
1 = inverted (180 degrees phase shift)
Left DAC output polarity:
0 = non-inverted
0
Output Signal
Path
1 = inverted (180 degrees phase shift)
11 (0Bh)
N/A
DAC left and DAC right volume do not update
until a 1 is written to DACVU (in reg 11 or 12)
Digital to
Analogue
Converter
(DAC)
PP, Rev 3.4, October 2006
95
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
