Pre-Production
WM8985
REGISTER
ADDRESS
BIT
LABEL
DLRSWAP
DEFAULT
DESCRIPTION
REFER TO
2
0
Controls whether DAC data appears in ‘right’ or
‘left’ phases of LRC clock:
Digital Audio
Interfaces
0=DAC data appear in ‘left’ phase of LRC
1=DAC data appears in ‘right’ phase of LRC
1
0
ALRSWAP
MONO
0
0
Controls whether ADC data appears in ‘right’ or
‘left’ phases of LRC clock:
Digital Audio
Interfaces
0=ADC data appear in ‘left’ phase of LRC
1=ADC data appears in ‘right’ phase of LRC
Selects between stereo and mono device
operation:
Digital Audio
Interfaces
0=Stereo device operation
1=Mono device operation. Data appears in ‘left’
phase of LRC
5 (05h)
8:6
5
000
0
Reserved. Initialise to 0
Companding Control 8-bit mode
0=off
WL8
Digital Audio
Interfaces
1=device operates in 8-bit mode
DAC companding
00=off (linear mode)
01=reserved
4:3
2:1
DAC_COMP
00
00
Digital Audio
Interfaces
10=µ-law
11=A-law
ADC_COMP
ADC companding
00=off (linear mode)
01=reserved
Digital Audio
Interfaces
10=µ-law
11=A-law
0
LOOPBACK
CLKSEL
0
Digital loopback function
0=No loopback
Digital Audio
Interfaces
1=Loopback enabled, ADC data output is fed
directly into DAC data input.
6 (06h)
8
1
Controls the source of the clock for all internal
operation:
Digital Audio
Interfaces
0=MCLK
1=PLL output
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or PLL
clock output (under control of CLKSEL)
Digital Audio
Interfaces
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
PP, Rev 3.4, October 2006
93
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
