欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM8985 参数 Datasheet PDF下载

WM8985图片预览
型号: WM8985
PDF下载: 下载PDF文件 查看货源
内容描述: 多媒体编解码器, D类耳机和线路输出 [Multimedia CODEC With Class D Headphone and Line Out]
分类和应用: 解码器编解码器
文件页数/大小: 118 页 / 1498 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM8985的Datasheet PDF文件第92页浏览型号WM8985的Datasheet PDF文件第93页浏览型号WM8985的Datasheet PDF文件第94页浏览型号WM8985的Datasheet PDF文件第95页浏览型号WM8985的Datasheet PDF文件第97页浏览型号WM8985的Datasheet PDF文件第98页浏览型号WM8985的Datasheet PDF文件第99页浏览型号WM8985的Datasheet PDF文件第100页  
WM8985  
Pre-Production  
REGISTER  
ADDRESS  
BIT  
LABEL  
DACVOLL  
DEFAULT  
DESCRIPTION  
REFER TO  
7:0  
11111111  
Left DAC Digital Volume Control  
0000 0000 = Digital Mute  
0000 0001 = -127dB  
Digital to  
Analogue  
Converter  
(DAC)  
0000 0010 = -126.5dB  
... 0.5dB steps up to  
1111 1111 = 0dB  
12 (0Ch)  
8
DACVU  
N/A  
DAC left and DAC right volume do not update  
until a 1 is written to DACVU (in reg 11 or 12)  
Output Signal  
Path  
7:0  
DACVOLR  
11111111  
Right DAC Digital Volume Control  
0000 0000 = Digital Mute  
0000 0001 = -127dB  
Output Signal  
Path  
0000 0010 = -126.5dB  
... 0.5dB steps up to  
1111 1111 = 0dB  
13 (0Dh)  
8
0
Reserved. Initialise to 0  
7:4  
JD_EN1  
JD_EN0  
0000  
Output enabled when selected jack detection  
input is logic 1  
Output  
Switching  
(Jack Detect)  
[4]= OUT1_EN_1  
[5]= OUT2_EN_1  
[6]= OUT3_EN_1  
[7]= OUT4_EN_1  
3:0  
0000  
Output enabled when selected jack detection  
input is logic 0.  
Output  
Switching  
(Jack Detect)  
[0]= OUT1_EN_0  
[1]= OUT2_EN_0  
[2]= OUT3_EN_0  
[3]= OUT4_EN_0  
14 (0Eh)  
8
HPFEN  
1
Analogue to  
Digital  
Converter  
(ADC)  
High Pass Filter Enable  
0=disabled  
1=enabled  
7
HPFAPP  
HPFCUT  
0
Select audio mode or application mode  
0=Audio mode (1st order, fc = ~3.7Hz)  
1=Application mode (2nd order, fc = HPFCUT)  
Analogue to  
Digital  
Converter  
(ADC)  
6:4  
3
000  
0
Application mode cut-off frequency  
See Figure 15 for details.  
Analogue to  
Digital  
Converter  
(ADC)  
ADCOSR  
128  
ADC oversample rate select  
0 = 64x (lowest power)  
1 = 128x (best SNR)  
Reserved. Initialise to 0  
ADC right channel polarity adjust:  
0=normal  
Power  
Management  
2
1
0
0
ADCRPOL  
ADCLPOL  
ADCVU  
Analogue to  
Digital  
Converter  
(ADC)  
1=inverted  
0
8
0
ADC left channel polarity adjust:  
0=normal  
Analogue to  
Digital  
Converter  
(ADC)  
1=inverted  
15 (0Fh)  
N/A  
ADC left and ADC right volume do not update  
until a 1 is written to ADCVU (in reg 16 or 17)  
Analogue to  
Digital  
Converter  
(ADC)  
PP, Rev 3.4, October 2006  
96  
w
 复制成功!