Pre-Production
WM8985
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
N/A
DESCRIPTION
REFER TO
0 (00h)
[8:0] RESET
8
Software reset
Resetting the
Chip
1 (01h)
0
0
Reserved. Initialise to 0
OUT4 mixer enable
0=disabled
7
6
5
OUT4MIXEN
Power
Management
1=enabled
OUT3MIXEN
PLLEN
0
0
OUT3 mixer enable
0=disabled
Power
Management
1=enabled
PLL enable
Master Clock
and Phase
Locked Loop
(PLL)
0=PLL off
1=PLL on
4
MICBEN
BIASEN
0
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Input Signal
Path
3
0
Analogue amplifier bias control
0=disabled
Power
Management
1=enabled
2
BUFIOEN
VMIDSEL
0
Unused input/output tie off buffer enable
0=disabled
Power
Management
1=enabled
1:0
00
Reference string impedance to VMID pin
00=off (open circuit)
01=75kΩ
Power
Management
10=300kΩ
11=5kΩ
2 (02h)
8
7
ROUT1EN
LOUT1EN
0
0
ROUT1 output enable
0=disabled
Power
Management
1=enabled
LOUT1 output enable
0=disabled
Power
Management
1=enabled
6
5
SLEEP
0
0
0 = normal device operation
Power
Management
1 = residual current reduced in device standby
mode
BOOSTENR
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Power
Management
4
3
2
BOOSTENL
INPPGAENR
INPPGAENL
0
0
0
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Power
Management
Right channel input PGA enable
0 = disabled
Power
Management
1 = enabled
Left channel input PGA enable
0 = disabled
Power
Management
1 = enabled
PP, Rev 3.4, October 2006
91
w