WM8985
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
BCLKDIV
DEFAULT
000
DESCRIPTION
REFER TO
4:2
Configures the BCLK output frequency, for use
when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
Digital Audio
Interfaces
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
1
0
0
0
Reserved. Initialise to 0
MS
Sets the chip to be master over LRC and BCLK
0=BCLK and LRC clock are inputs
Digital Audio
Interfaces
1=BCLK and LRC clock are outputs generated
by the WM8978 (MASTER)
7 (07h)
8
M128ENB
DCLKDIV
0
0 = low power mode enabled
1 = low power mode disabled
Additional
Control
7:4
1000
Controls clock division from SYSCLK to
generate suitable class D clock.
Class A / D
Headphone
Outputs
Recommended class D clock frequency =
1.4MHz.
0000 = divide by 1
0010 = divide by 2
0011 = divide by 3
0100 = divide by 4
0101 = divide by 5.5
0110 = divide by 6
1000 = divide by 8
1001 = divide by 12
1010 = divide by 16
3:1
SR
000
Approximate sample rate (configures the
coefficients for the internal digital filters):
Audio Sample
Rates
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
0
SLOWCLKEN
0
Slow clock enable. Used for both the jack insert
detect debounce circuit and the zero cross
timeout.
Analogue
Outputs
0 = slow clock disabled
1 = slow clock enabled
GPIO1 Open drain enable
0 = Open drain disabled
1 = Open drain enabled
8 (08h)
8
7
6
GPIO1GP
0
0
0
General
Purpose
Input/Output
(GPIO)
GPIO1GPU
GPIO1GPD
GPIO1 Internal pull-up enable:
0 = Internal pull-up disabled
1 = Internal pull-up enabled
General
Purpose
Input/Output
(GPIO)
GPIO1 Internal pull-down enable:
0 = Internal pull-down disabled
1 = Internal pull-down enabled
General
Purpose
Input/Output
(GPIO)
PP, Rev 3.4, October 2006
94
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
