WM8961
Pre-Production
AUTOMATIC MODE V’S MANUAL MODE CLOCK CONFIGURATION
The clock configuration for the WM8961 can be set automatically or manually (default). The mode of
operation is set by MANUAL_MODE, R30[0].
In manual mode the user must configure all the clock registers (described in the following paragraphs)
manually.
In automatic mode, SAMPLE_RATE and CLK_SYS_RATE are used to configure the following
registers automatically: CLK_256_DIV, CLK_TO_DIV, ADCDIV, DACDIV, CLK_DCS_DIV and
DCLKDIV. The BCLKDIV and LRCLK_RATE still require to be set manually in this mode.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Manual clock configuration Enable
R30 (1Eh)
Clocking 3
0
MANUAL_MODE
1
0 = When low, use SAMPLE_RATE & CLK_SYS_RATE to
allow automatic configuration of system clock dividers.
Excludes master mode audio interface clocks.
1 = manual configuration of system clock dividers.
256kHz clock divider setting
000000 : SYSCLK/1
000001 : SYSCLK/2
…
101111 : SYSCLK/48 (default)
…
6:1
2:0
4:1
CLK_256K_DIV[5:0]
SAMPLE_RATE[2:0]
CLK_SYS_RATE[3:0]
10111
111110 : SYSCLK/63
111111 : SYSCLK/64
R27 (1Bh)
Additional
Control (3)
000
Sample Rate Control for ALC and automatic configuration
000 : 44.1k/48k
001 : 32k
010 : 22.05k/24k
011 : 16k
100 : 11.25k/12k
101 : 8k
110-111 : reserved
Specifies the rate of SYSCLK with respect to the sample
rate.
R56 (38h)
Clocking 4
0011
0000 : 64*fs
0001 : 128*fs
0010 : 192*fs
0011 : 256*fs
0100 : 384*fs
0101 : 512*fs
0110 : 768*fs
0111 : 1024 *fs
1000 : 1408*fs
1001: 1536*fs
1010 -> 1111 : reserved
Table 52 Clock Configuration: Automatic v’s Manual
PP, August 2009, Rev 3.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
