WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Defines the ADC 256fs clock, which is further divided by 2.
000 : 256fs = SYSCLK / 1.0 (default =12.288MHz, fs= 48 KHz)
001 : Reserved
R4 (04h)
Clocking1
8:6
ADCDIV[2:0]
000
010 : 256fs = SYSCLK / 2
011 : 256fs = SYSCLK / 3
100 : 256fs = SYSCLK / 4
101 : 256fs = SYSCLK / 5.5
110 : 256fs = SYSCLK / 6
111 : Reserved
Defines the DAC clock.
5:3
DACDIV[2:0]
100
000 : DAC clock = SYSCLK / 1
001 : Reserved
010 : DAC clock = SYSCLK / 2
011 : DAC clock = SYSCLK / 3
100 : DAC clock = SYSCLK / 4 (default =3.072 MHz when
SYSCLK=12.288MHz)
101 : DAC clock = SYSCLK / 5.5
110 : DAC clock = SYSCLK / 6
111 : Reserved
BCLK Frequency (Master Mode)
0000 = SYSCLK
R8 (08h)
Clocking2
3:0
BCLKDIV[3:0]
0100
0001 = Reserved
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4 (default)
0101 = Reserved
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = Reserved
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 24
1100 = Reserved
1101 to 1111 = SYSCLK / 32
Integer divide of BCLK. 50:50 LRCLK duty cycle is only
guaranteed with even values (4, 6, … … , 510).
R14 (0Eh)
Audio Interface
2
8:0
LRCLK_RATE[8:0] 0_0100_0000
0_0000_0000 to 0_0000_0011 : reserved
0_0000_0100 : 4
…
0_0100_0000 : 64
…
1_1111_1110 : 510
1_1111_1111: Reserved
Table 54 ADC, DAC and Master Mode BCLK and LRC Control
PP, August 2009, Rev 3.1
w
74
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
