WM8961
Pre-Production
EXAMPLE SAMPLE RATE CONFIGURATIONS
Using the registers shown in Table 51, some example ADCDIV and DACDIV settings have been
calculated and detailed in Table 52 for various sample rates and SYSCLKs.
ADC / RECOMMENDED
DACDIV
ADCDIV
DAC
SAMPLE
RATE
SYSCLK
(MHZ)
(kHz)
48
12.288
100 => DAC clk = 12.288 MHz/4.0 = 3.072MHz (=64fs)
100 => DAC clk = 8.192 MHz/4.0 = 2.048MHz (=64fs)
010 => DAC clk = 6.144 MHz/2.0 = 3.072MHz (=128fs)
000 => DAC clk = 3.072 MHz/1.0 = 3.072MHz (=256fs)
100 => DAC clk = 11.2896MHz/4.0 = 2.8224MHz (=64fs)
010 => DAC clk = 5.6448 MHz/2.0 = 2.8224MHz (=128fs)
000 => DAC clk = 3.072 MHz/1.0 = 3.072MHz (=384fs)
000 => 256fs = 12.288 MHz/1.0 =12.288 MHz
000 => 256fs = 8.192 MHz/1.0 = 8.192 MHz
000 => 256fs = 6.144 MHz/ 1.0 = 6.144 MHz
000 => 256fs = 3.072 MHz/ 1.0 = 3.072 MHz
000 => 256fs = 11.2896MHz/1.0 =11.2896MHz
000 => 256fs = 5.6448 MHz/1.0 =5.6448 MHz
000 => 256fs = 3.072 MHz/ 1.0 = 3.072 MHz
32
8.192
24
6.144
12
3.072
44.1
22.05
8
11.2896
5.6448
3.072
Table 55 ADC and DAC Recommended DACDIV and ADCDIV Configuration
If only the DAC is being used (ADC not used) then the SYSCLK can be reduced to save power. This
is shown in Table 56.
DAC SAMPLE RATE (kHz) RECOMMENDED SYSCLK
(MHZ)
DACDIV
48
3.072
2.048
3.072
3.072
2.8224
2.8224
3.072
000 => DAC clk = 3.072 MHz /1.0 = 3.072 MHz
(=64fs)
32
000 => DAC clk = 2.048 MHz/1.0 = 2.048 MHz
(=64fs)
24
000 => DAC clk = 3.072 MHz/1.0 = 3.072 MHz
(=128fs)
12
000 => DAC clk = 3.072 MHz/1.0 = 3.072 MHz
(=256fs)
44.1
22.05
8
000 => DAC clk = 2.8224 MHz/1.0 = 2.8224
MHz (=64fs)
000 => DAC clk = 2.8224 MHz/1.0 =
2.8224MHz (=128fs)
000 => DAC clk = 3.072 MHz/1.0 = 3.072MHz
(=384fs)
Table 56 Recommended DACDIV Configuration for DAC Playback Only
PP, August 2009, Rev 3.1
w
75
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
