WM8961
Pre-Production
MASTER MODE BCLK CONFIGURATION
The ADC and DAC must be configured to operate at the same sample rate. In master mode the BCLK
and LRCLK_RATE must be configured to support this sample rate. The following Table 57 shows
example calculations of the maximum word length supported for the ADC and DAC running at
different sample rates. Note that ADCDIV, DACDIV and LRCLK_RATE must be configured to be the
same sample rate.
SYSCLK
(MHz)
SAMPLE
RATE
LRCLKRATE
BCLKDIV
0000 (=1)
0100 (=4)
0000 (=1)
0110 (=6)
BCLK RATE
(MASTER MODE)
(MHz)
MAXIMUM WORD LENGTH (AT
ADC/DAC SAMPLE RATE)
fs=48 kHz
0x100
=BCLK/256 = 48 kHz
12.288
(12.288 MHz/48 kHz) / 2
= 128.
=> 32 bit word length supported.
0x040
= BCLK/64 = 48 kHz
3.072
(3.072 MHz/48 kHz) / 2
= 32.
=> 32 bit word length supported.
Fs=32 kHz
0x180
=BCLK/384 = 32 kHz
12.288
2.048
(12.288 MHz/32 kHz) / 2
= 192.
=> 32 bit word length supported.
12.288
0x040
= BCLK/64 = 32 kHz
(2.048 MHz/32 kHz) / 2
= 32.
=> 32 bit word length supported.
0x020
= BCLK/32 = 32 kHz
1001 (=12)
0000 (=1)
0100 (=4)
0100 (=4)
1.024
(1.024 MHz/32 kHz) / 2
= 16.
=> 16 bit word length supported.
fs=44.1 kHz 0x100
=BCLK/256 = 44.1
11.2896
2.8224
2.8224
(11.2896MHz/44.1 kHz) / 2
= 128.
=> 32 bit word length supported.
kHz
0x040
= BCLK/64 = 44.1
kHz
(2.8224MHz/44.1 kHz) / 2
= 32.
=> 32 bit word length supported.
11.2896
Fs=22.05
kHz
0x080
=BCLK/128 = 22.05
kHz
(2.8224MHz/22.05 kHz) / 2
= 64.
=> 32 bit word length supported.
Table 57 ADC and DAC Maximum Word Lengths Based on Valid BCLK (master mode) Configuration
PP, August 2009, Rev 3.1
w
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
