WM8961
Pre-Production
WM8961
REG
WSEQ
CUMULATIVE STARTUP
_LOCATION _INDEX
EOS
1’b0
WIDTH START DATA
DELAY
COMMENT
Clear RMV_SHRT on
outputs
DELAY
TIME
30
8’h45
3’h4
4’h3
8’h0E
4’h0
0.0005
0.0180
Clear
HPL_ENA_OUTP &
HPR_ENA_OUTP
31
32
33
34
35
36
37
8’h45
8’h02
8’h03
8’h03
8’h28
8’h29
8’h29
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
3’h4
3’h6
3’h6
3’h0
3’h6
3’h6
3’h0
4’h2
4’h0
4’h0
4’h8
4’h0
4’h0
4’h8
8’h0C
8’h00
8’h00
8’h01
8’h00
8’h00
8’h01
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
0.0005
0.0005
0.0005
0.0005
0.0005
0.0005
0.0005
0.0185
0.0190
0.0195
0.0200
0.0205
0.0210
0.0215
LOUTVOL to mute
ROUTVOL to mute
OUT1VU
SPKLVOL to mute
SPKRVOL to mute
SPKVU
Disable Servo on
inputs
Disable Servo on
outputs
38
39
8’h3C
8’h3D
1’b0
1’b0
3’h4
3’h4
4’h3
4’h3
8’h00
8’h00
4’h0
4’h0
0.0005
0.0005
0.0220
0.0225
SPKL_PGA = 0,
SPKR_PGA = 0,
LOUT1_PGA = 0,
ROUT1_PGA = 0,
DACL = 0, DACR = 0
40
41
8’h1A
8’h31
1’b0
1’b0
3’h5
3’h1
4’h3
4’h6
8’h00
8’h00
4’h0
4’h0
0.0005
0.0005
0.0230
0.0235
Disable Class D
Disable HPL_ENA,
HPR_ENA,
HPL_ENA_DLY,
HPR_ENA_DLY
42
43
8’h45
8’h48
1’b0
1’b0
3’h5
3’h0
4’h0
4’h0
8’h00
8’h00
4’h0
4’h0
0.0005
0.0005
0.0240
0.0245
Disable Charge Pump
VREF = 0 ; ADCL = 0 ;
ADCR = 0 ; MICB = 0 ;
AINL = 0 ; AINR = 0
BUFDCOPEN = 0,
BUFIOEN = 0 ;
44
8’h19
1’b0
3’h5
4’h1
8’h00
4’h0
0.0005
0.0250
Disable current bias
circuits
45
8’h1C
1’b0
3’h1
4’h3
8’h00
4’h0
0.0005
0.0255
VMIDSEL = 00,
46
47
8’h19
8’h08
1’b0
1’b0
3’h1
3’h0
4’h7
4’h4
8’h00
8’h00
4’h0
4’h0
disable VMID
0.0005
0.0005
0.0260
0.0265
CLK_DSP_ENA = 0
Dummy Write for
expansion
48
8’hFE
1’b1
3’h0
4’h0
8’h00
4’h0
0.0005
0.0270
Table 50 Write Sequencer Default Values (RAM =Locations 0-31, ROM = Locations 32-48)
PP, August 2009, Rev 3.1
w
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
