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WM8955L
AUDIO SAMPLE RATES
The WM8955L supports a wide range of master clock frequencies on the MCLK pin, and can
generate manycommonlyused audio sample rates directlyfrom the master clock.
There are two clocking modes:
•
•
‘Normal’ mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and runs without a PLL.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Clocking Mode Select
R8 (08h)
Sample Rates
0
USB
0
1: USB Mode
0: ‘Normal’ Mode
Sample Rate Control
MCLK Divide by2
0: Divide disabled
1: Divide enabled
MCLK Divide by2
0: Divide disabled
1: Divide enabled
5:1
6
SR [4:0]
0000
0
MCLK
DIV2
7
CLKOUT
DIV2
0
Table 22 Clocking andSample Rate Control
The clocking of the WM8955L is controlled using the MCLKDIV2, USB, and SR control bits. Setting
the MCLKDIV2 bit divides MCLK bytwo internally. The USB bit selects between ‘Normal’ and USB
mode. Each combination of the SR4 to SR0 control bits selects one MCLK division ratio and hence
one sample rate (see next page). The digital filter characteristics are automaticallyadjusted to suit
the MCLK and sample rate selected (see Digital Filter Characteristics).
Since all sample rates are generated bydividing MCLK, their accuracydepends on the accuracyof
MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates
(e.g. 44.1kHz in USB mode) are approximated, i.e. theydiffer from their target value bya verysmall
amount. This is not audible, as the maximum deviation is only0.27% (8.0214kHz instead of 8kHz in
USB mode - for comparison, a half-tone step corresponds to a 5.9% change in pitch).
Product Preview Rev 0.4 May2003
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
