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WM8955L
MASTER CLOCK AND PHASE LOCKED LOOP
The WM8955L has an on-chip phase-locked loop (PLL) circuit that can be used to:
•
generate a master clock for the WM9755L audio function from another external clock,
e.g. in telecoms applications.
•
generate a clock for another part of the system from an existing audio master clock.
The PLL circuit is shown below.
MCLK
SEL
MCLK
DIV2
PLL
PLLOUT
DIV2
DIGITAL
CORE
MCLK
f/2
f/4
f/2
R = f2 / f1
f1
f2
CLKOUT
SEL
CLKOUTEN
CLKOUT
DIV2
CLKOUT
f/2
Figure TBD PLL circuit
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
8
CLKOUTDIV2
0
CLKOUT Divide by2
Sample Rates
0: Divide disabled
1: Divide enabled
MCLK Divide by2
0: Divide disabled
1: Divide enabled
Select internal master clock
0: from MCLK pin
6
8
7
6
5
MCLKDIV2
0
R43 (2Bh)
MCLKSEL
0
Clocking and
PLL
1: from PLL (make sure PLLEN=1)
CLKOUT Enable
CLKOUTEN
CLKOUTSEL
PLLOUTDIV2
0
0: Pin disabled (tri-state)
1: Pin Enabled
0
Select source of CLKOUT
0: from MCLK pin
1: from PLL (make sure PLLEN=1)
PLL Output Divide by2
0: Divide disabled
TBD
1: Divide enabled
4
3
PLL_RB
PLLEN
TBD
0
TBD
PLL Enable
0: PLL disabled; 1: PLL enabled.
Table 19 PLL andClocking Control
Product Preview Rev 0.4 May2003
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
